Lines Matching refs:bsev
120 err = readl_relaxed_poll_timeout(vde->bsev + INTR_STATUS, value, in tegra_vde_wait_bsev()
127 err = readl_relaxed_poll_timeout(vde->bsev + INTR_STATUS, value, in tegra_vde_wait_bsev()
137 err = readl_relaxed_poll_timeout(vde->bsev + INTR_STATUS, value, in tegra_vde_wait_bsev()
150 tegra_vde_writel(vde, value, vde->bsev, ICMDQUE_WR); in tegra_vde_push_to_bsev_icmdqueue()
283 tegra_vde_set_bits(vde, 0x000B, vde->bsev, CMDQUE_CONTROL); in tegra_vde_setup_hw_context()
303 tegra_vde_writel(vde, 0x0003FC00, vde->bsev, INTR_STATUS); in tegra_vde_setup_hw_context()
304 tegra_vde_writel(vde, 0x0000150D, vde->bsev, BSE_CONFIG); in tegra_vde_setup_hw_context()
305 tegra_vde_writel(vde, 0x00000100, vde->bsev, BSE_INT_ENB); in tegra_vde_setup_hw_context()
306 tegra_vde_writel(vde, 0x00000000, vde->bsev, 0x98); in tegra_vde_setup_hw_context()
307 tegra_vde_writel(vde, 0x00000060, vde->bsev, 0x9C); in tegra_vde_setup_hw_context()
324 tegra_vde_writel(vde, 0x00000000, vde->bsev, 0x8C); in tegra_vde_setup_hw_context()
326 vde->bsev, 0x54); in tegra_vde_setup_hw_context()
332 tegra_vde_writel(vde, value, vde->bsev, 0x88); in tegra_vde_setup_hw_context()
463 tegra_vde_writel(vde, 0x00000001, vde->bsev, 0x8C); in tegra_vde_decode_frame()
637 bsev_ptr = tegra_vde_readl(vde, vde->bsev, 0x10); in tegra_vde_decode_end()