Lines Matching refs:mbe
57 return readl_relaxed_poll_timeout(vde->mbe + 0x8C, tmp, in tegra_vde_wait_mbe()
70 tegra_vde_writel(vde, 0xD0000000 | (0 << 23), vde->mbe, 0x80); in tegra_vde_setup_mbe_frame_idx()
71 tegra_vde_writel(vde, 0xD0200000 | (0 << 23), vde->mbe, 0x80); in tegra_vde_setup_mbe_frame_idx()
82 vde->mbe, 0x80); in tegra_vde_setup_mbe_frame_idx()
84 vde->mbe, 0x80); in tegra_vde_setup_mbe_frame_idx()
93 tegra_vde_writel(vde, value, vde->mbe, 0x80); in tegra_vde_setup_mbe_frame_idx()
109 vde->mbe, 0x80); in tegra_vde_mbe_set_0xa_reg()
111 vde->mbe, 0x80); in tegra_vde_mbe_set_0xa_reg()
284 tegra_vde_set_bits(vde, 0x8002, vde->mbe, 0x50); in tegra_vde_setup_hw_context()
285 tegra_vde_set_bits(vde, 0x000A, vde->mbe, 0xA0); in tegra_vde_setup_hw_context()
297 tegra_vde_writel(vde, 0x00000000, vde->mbe, 0x84); in tegra_vde_setup_hw_context()
409 tegra_vde_writel(vde, value, vde->mbe, 0x80); in tegra_vde_setup_hw_context()
416 tegra_vde_writel(vde, value, vde->mbe, 0x80); in tegra_vde_setup_hw_context()
418 tegra_vde_writel(vde, 0xF4000001, vde->mbe, 0x80); in tegra_vde_setup_hw_context()
419 tegra_vde_writel(vde, 0x20000000, vde->mbe, 0x80); in tegra_vde_setup_hw_context()
420 tegra_vde_writel(vde, 0xF4000101, vde->mbe, 0x80); in tegra_vde_setup_hw_context()
425 tegra_vde_writel(vde, value, vde->mbe, 0x80); in tegra_vde_setup_hw_context()
447 tegra_vde_writel(vde, value, vde->mbe, 0x80); in tegra_vde_setup_hw_context()