Lines Matching refs:reg_w
49 static void reg_w(struct sd *sd, u16 index, u16 value);
157 reg_w(sd, 0x39, 0x0010); /* JPEG clock enable */ in w9968cf_upload_quantizationtables()
162 reg_w(sd, 0x40 + i, a); in w9968cf_upload_quantizationtables()
163 reg_w(sd, 0x60 + i, b); in w9968cf_upload_quantizationtables()
165 reg_w(sd, 0x39, 0x0012); /* JPEG encoder enable */ in w9968cf_upload_quantizationtables()
342 reg_w(sd, 0x00, 0xff00); /* power-down */ in w9968cf_configure()
343 reg_w(sd, 0x00, 0xbf17); /* reset everything */ in w9968cf_configure()
344 reg_w(sd, 0x00, 0xbf10); /* normal operation */ in w9968cf_configure()
345 reg_w(sd, 0x01, 0x0010); /* serial bus, SDS high */ in w9968cf_configure()
346 reg_w(sd, 0x01, 0x0000); /* serial bus, SDS low */ in w9968cf_configure()
347 reg_w(sd, 0x01, 0x0010); /* ..high 'beep-beep' */ in w9968cf_configure()
348 reg_w(sd, 0x01, 0x0030); /* Set sda scl to FSB mode */ in w9968cf_configure()
363 reg_w(sd, 0x00, 0xff00); /* power off */ in w9968cf_init()
364 reg_w(sd, 0x00, 0xbf10); /* power on */ in w9968cf_init()
366 reg_w(sd, 0x03, 0x405d); /* DRAM timings */ in w9968cf_init()
367 reg_w(sd, 0x04, 0x0030); /* SDRAM timings */ in w9968cf_init()
369 reg_w(sd, 0x20, y0 & 0xffff); /* Y buf.0, low */ in w9968cf_init()
370 reg_w(sd, 0x21, y0 >> 16); /* Y buf.0, high */ in w9968cf_init()
371 reg_w(sd, 0x24, u0 & 0xffff); /* U buf.0, low */ in w9968cf_init()
372 reg_w(sd, 0x25, u0 >> 16); /* U buf.0, high */ in w9968cf_init()
373 reg_w(sd, 0x28, v0 & 0xffff); /* V buf.0, low */ in w9968cf_init()
374 reg_w(sd, 0x29, v0 >> 16); /* V buf.0, high */ in w9968cf_init()
376 reg_w(sd, 0x22, y1 & 0xffff); /* Y buf.1, low */ in w9968cf_init()
377 reg_w(sd, 0x23, y1 >> 16); /* Y buf.1, high */ in w9968cf_init()
378 reg_w(sd, 0x26, u1 & 0xffff); /* U buf.1, low */ in w9968cf_init()
379 reg_w(sd, 0x27, u1 >> 16); /* U buf.1, high */ in w9968cf_init()
380 reg_w(sd, 0x2a, v1 & 0xffff); /* V buf.1, low */ in w9968cf_init()
381 reg_w(sd, 0x2b, v1 >> 16); /* V buf.1, high */ in w9968cf_init()
383 reg_w(sd, 0x32, y1 & 0xffff); /* JPEG buf 0 low */ in w9968cf_init()
384 reg_w(sd, 0x33, y1 >> 16); /* JPEG buf 0 high */ in w9968cf_init()
386 reg_w(sd, 0x34, y1 & 0xffff); /* JPEG buf 1 low */ in w9968cf_init()
387 reg_w(sd, 0x35, y1 >> 16); /* JPEG bug 1 high */ in w9968cf_init()
389 reg_w(sd, 0x36, 0x0000);/* JPEG restart interval */ in w9968cf_init()
390 reg_w(sd, 0x37, 0x0804);/*JPEG VLE FIFO threshold*/ in w9968cf_init()
391 reg_w(sd, 0x38, 0x0000);/* disable hw up-scaling */ in w9968cf_init()
392 reg_w(sd, 0x3f, 0x0000); /* JPEG/MCTL test data */ in w9968cf_init()
444 reg_w(sd, 0x10, start_cropx + x); in w9968cf_set_crop_window()
445 reg_w(sd, 0x11, start_cropy + y); in w9968cf_set_crop_window()
446 reg_w(sd, 0x12, start_cropx + x + cw); in w9968cf_set_crop_window()
447 reg_w(sd, 0x13, start_cropy + y + ch); in w9968cf_set_crop_window()
456 reg_w(sd, 0x14, sd->gspca_dev.pixfmt.width); in w9968cf_mode_init_regs()
457 reg_w(sd, 0x15, sd->gspca_dev.pixfmt.height); in w9968cf_mode_init_regs()
460 reg_w(sd, 0x30, sd->gspca_dev.pixfmt.width); in w9968cf_mode_init_regs()
461 reg_w(sd, 0x31, sd->gspca_dev.pixfmt.height); in w9968cf_mode_init_regs()
466 reg_w(sd, 0x2c, sd->gspca_dev.pixfmt.width / 2); in w9968cf_mode_init_regs()
467 reg_w(sd, 0x2d, sd->gspca_dev.pixfmt.width / 4); in w9968cf_mode_init_regs()
469 reg_w(sd, 0x2c, sd->gspca_dev.pixfmt.width); in w9968cf_mode_init_regs()
471 reg_w(sd, 0x00, 0xbf17); /* reset everything */ in w9968cf_mode_init_regs()
472 reg_w(sd, 0x00, 0xbf10); /* normal operation */ in w9968cf_mode_init_regs()
476 reg_w(sd, 0x3d, val & 0xffff); /* low bits */ in w9968cf_mode_init_regs()
477 reg_w(sd, 0x3e, val >> 16); /* high bits */ in w9968cf_mode_init_regs()
518 reg_w(sd, 0x16, val); in w9968cf_mode_init_regs()
526 reg_w(sd, 0x39, 0x0000); /* disable JPEG encoder */ in w9968cf_stop0()
527 reg_w(sd, 0x16, 0x0000); /* stop video capture */ in w9968cf_stop0()