Lines Matching refs:zq
309 u32 zq = 0, val = 0; in get_zq_config_reg() local
312 zq |= val << ZQ_REFINTERVAL_SHIFT; in get_zq_config_reg()
315 zq |= val << ZQ_ZQCL_MULT_SHIFT; in get_zq_config_reg()
318 zq |= val << ZQ_ZQINIT_MULT_SHIFT; in get_zq_config_reg()
320 zq |= ZQ_SFEXITEN_ENABLE << ZQ_SFEXITEN_SHIFT; in get_zq_config_reg()
323 zq |= ZQ_DUALCALEN_ENABLE << ZQ_DUALCALEN_SHIFT; in get_zq_config_reg()
325 zq |= ZQ_DUALCALEN_DISABLE << ZQ_DUALCALEN_SHIFT; in get_zq_config_reg()
327 zq |= ZQ_CS0EN_MASK; /* CS0 is used for sure */ in get_zq_config_reg()
330 zq |= val << ZQ_CS1EN_SHIFT; in get_zq_config_reg()
332 return zq; in get_zq_config_reg()
715 u32 pwr_mgmt_ctrl, zq, temp_alert_cfg; in emif_onetime_settings() local
734 zq = get_zq_config_reg(addressing, device_info->cs1_used, in emif_onetime_settings()
736 writel(zq, base + EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG); in emif_onetime_settings()