Lines Matching refs:target_rate
289 unsigned long target_rate) in find_target_freq_idx() argument
294 if (dmc->opp[i].freq_hz <= target_rate) in find_target_freq_idx()
415 unsigned long target_rate) in exynos5_dram_change_timings() argument
420 if (dmc->opp[idx].freq_hz <= target_rate) in exynos5_dram_change_timings()
505 unsigned long target_rate) in exynos5_dmc_align_bypass_dram_timings() argument
507 int idx = find_target_freq_idx(dmc, target_rate); in exynos5_dmc_align_bypass_dram_timings()
530 unsigned long target_rate, in exynos5_dmc_switch_to_bypass_configuration() argument
547 ret = exynos5_dmc_align_bypass_dram_timings(dmc, target_rate); in exynos5_dmc_switch_to_bypass_configuration()
584 unsigned long target_rate, in exynos5_dmc_change_freq_and_volt() argument
589 ret = exynos5_dmc_switch_to_bypass_configuration(dmc, target_rate, in exynos5_dmc_change_freq_and_volt()
611 exynos5_dram_change_timings(dmc, target_rate); in exynos5_dmc_change_freq_and_volt()
613 clk_set_rate(dmc->fout_bpll, target_rate); in exynos5_dmc_change_freq_and_volt()
654 unsigned long *target_rate, in exynos5_dmc_get_volt_freq() argument
663 *target_rate = dev_pm_opp_get_freq(opp); in exynos5_dmc_get_volt_freq()
686 unsigned long target_rate = 0; in exynos5_dmc_target() local
690 ret = exynos5_dmc_get_volt_freq(dmc, freq, &target_rate, &target_volt, in exynos5_dmc_target()
696 if (target_rate == dmc->curr_rate) in exynos5_dmc_target()
701 ret = exynos5_dmc_change_freq_and_volt(dmc, target_rate, target_volt); in exynos5_dmc_target()
708 dmc->curr_rate = target_rate; in exynos5_dmc_target()
1258 unsigned long target_rate = 0; in exynos5_dmc_init_clks() local
1296 ret = exynos5_dmc_get_volt_freq(dmc, &dmc->curr_rate, &target_rate, in exynos5_dmc_init_clks()