Lines Matching refs:emc
518 static void emc_ccfifo_writel(struct tegra_emc *emc, u32 value, in emc_ccfifo_writel() argument
521 writel(value, emc->regs + EMC_CCFIFO_DATA); in emc_ccfifo_writel()
522 writel(offset, emc->regs + EMC_CCFIFO_ADDR); in emc_ccfifo_writel()
525 static void emc_seq_update_timing(struct tegra_emc *emc) in emc_seq_update_timing() argument
530 writel(1, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
533 value = readl(emc->regs + EMC_STATUS); in emc_seq_update_timing()
539 dev_err(emc->dev, "timing update timed out\n"); in emc_seq_update_timing()
542 static void emc_seq_disable_auto_cal(struct tegra_emc *emc) in emc_seq_disable_auto_cal() argument
547 writel(0, emc->regs + EMC_AUTO_CAL_INTERVAL); in emc_seq_disable_auto_cal()
550 value = readl(emc->regs + EMC_AUTO_CAL_STATUS); in emc_seq_disable_auto_cal()
556 dev_err(emc->dev, "auto cal disable timed out\n"); in emc_seq_disable_auto_cal()
559 static void emc_seq_wait_clkchange(struct tegra_emc *emc) in emc_seq_wait_clkchange() argument
565 value = readl(emc->regs + EMC_INTSTATUS); in emc_seq_wait_clkchange()
571 dev_err(emc->dev, "clock change timed out\n"); in emc_seq_wait_clkchange()
574 static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc, in tegra_emc_find_timing() argument
580 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_find_timing()
581 if (emc->timings[i].rate == rate) { in tegra_emc_find_timing()
582 timing = &emc->timings[i]; in tegra_emc_find_timing()
588 dev_err(emc->dev, "no timing for rate %lu\n", rate); in tegra_emc_find_timing()
595 static int tegra_emc_prepare_timing_change(struct tegra_emc *emc, in tegra_emc_prepare_timing_change() argument
598 struct emc_timing *timing = tegra_emc_find_timing(emc, rate); in tegra_emc_prepare_timing_change()
599 struct emc_timing *last = &emc->last_timing; in tegra_emc_prepare_timing_change()
617 writel(EMC_INTSTATUS_CLKCHANGE_COMPLETE, emc->regs + EMC_INTSTATUS); in tegra_emc_prepare_timing_change()
620 val = readl(emc->regs + EMC_CFG); in tegra_emc_prepare_timing_change()
623 writel(val, emc->regs + EMC_CFG); in tegra_emc_prepare_timing_change()
629 if (emc->dram_type == DRAM_TYPE_DDR3) in tegra_emc_prepare_timing_change()
634 val = readl(emc->regs + EMC_SEL_DPD_CTRL); in tegra_emc_prepare_timing_change()
637 writel(val, emc->regs + EMC_SEL_DPD_CTRL); in tegra_emc_prepare_timing_change()
641 val = readl(emc->regs + EMC_BGBIAS_CTL0); in tegra_emc_prepare_timing_change()
656 writel(val2, emc->regs + EMC_BGBIAS_CTL0); in tegra_emc_prepare_timing_change()
662 val = readl(emc->regs + EMC_XM2DQSPADCTRL2); in tegra_emc_prepare_timing_change()
676 writel(val, emc->regs + EMC_XM2DQSPADCTRL2); in tegra_emc_prepare_timing_change()
683 emc_seq_update_timing(emc); in tegra_emc_prepare_timing_change()
689 emc_seq_disable_auto_cal(emc); in tegra_emc_prepare_timing_change()
691 emc->regs + EMC_CTT_TERM_CTRL); in tegra_emc_prepare_timing_change()
692 emc_seq_update_timing(emc); in tegra_emc_prepare_timing_change()
698 emc->regs + emc_burst_regs[i]); in tegra_emc_prepare_timing_change()
700 writel(timing->emc_xm2dqspadctrl2, emc->regs + EMC_XM2DQSPADCTRL2); in tegra_emc_prepare_timing_change()
701 writel(timing->emc_zcal_interval, emc->regs + EMC_ZCAL_INTERVAL); in tegra_emc_prepare_timing_change()
703 tegra_mc_write_emem_configuration(emc->mc, timing->rate); in tegra_emc_prepare_timing_change()
706 emc_ccfifo_writel(emc, val, EMC_CFG); in tegra_emc_prepare_timing_change()
710 emc_ccfifo_writel(emc, timing->emc_auto_cal_config2, in tegra_emc_prepare_timing_change()
714 emc_ccfifo_writel(emc, timing->emc_auto_cal_config3, in tegra_emc_prepare_timing_change()
720 emc_ccfifo_writel(emc, val, EMC_AUTO_CAL_CONFIG); in tegra_emc_prepare_timing_change()
724 if (emc->dram_type == DRAM_TYPE_DDR3 && in tegra_emc_prepare_timing_change()
730 cnt -= emc->dram_num * 256; in tegra_emc_prepare_timing_change()
743 writel(val, emc->regs + EMC_MRS_WAIT_CNT); in tegra_emc_prepare_timing_change()
748 emc_ccfifo_writel(emc, val, EMC_CFG_2); in tegra_emc_prepare_timing_change()
751 if (emc->dram_type == DRAM_TYPE_DDR3 && dll_change == DLL_CHANGE_OFF) in tegra_emc_prepare_timing_change()
752 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS); in tegra_emc_prepare_timing_change()
755 emc_ccfifo_writel(emc, EMC_REFCTRL_DEV_SEL(emc->dram_num), in tegra_emc_prepare_timing_change()
757 if (emc->dram_type == DRAM_TYPE_DDR3) in tegra_emc_prepare_timing_change()
758 emc_ccfifo_writel(emc, EMC_DRAM_DEV_SEL(emc->dram_num) | in tegra_emc_prepare_timing_change()
763 emc_ccfifo_writel(emc, 1, EMC_STALL_THEN_EXE_AFTER_CLKCHANGE); in tegra_emc_prepare_timing_change()
766 if (emc->dram_type == DRAM_TYPE_DDR3) in tegra_emc_prepare_timing_change()
767 emc_ccfifo_writel(emc, EMC_DRAM_DEV_SEL(emc->dram_num), in tegra_emc_prepare_timing_change()
769 emc_ccfifo_writel(emc, EMC_REFCTRL_DEV_SEL(emc->dram_num) | in tegra_emc_prepare_timing_change()
774 if (emc->dram_type == DRAM_TYPE_DDR3) { in tegra_emc_prepare_timing_change()
776 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS); in tegra_emc_prepare_timing_change()
778 emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_EMRS2); in tegra_emc_prepare_timing_change()
789 emc_ccfifo_writel(emc, val, EMC_MRS); in tegra_emc_prepare_timing_change()
793 emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_MRW2); in tegra_emc_prepare_timing_change()
795 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_MRW); in tegra_emc_prepare_timing_change()
797 emc_ccfifo_writel(emc, timing->emc_mode_4, EMC_MRW4); in tegra_emc_prepare_timing_change()
802 emc_ccfifo_writel(emc, EMC_ZQ_CAL_LONG_CMD_DEV0, EMC_ZQ_CAL); in tegra_emc_prepare_timing_change()
803 if (emc->dram_num > 1) in tegra_emc_prepare_timing_change()
804 emc_ccfifo_writel(emc, EMC_ZQ_CAL_LONG_CMD_DEV1, in tegra_emc_prepare_timing_change()
809 emc_ccfifo_writel(emc, 0, EMC_CCFIFO_STATUS); in tegra_emc_prepare_timing_change()
812 emc_ccfifo_writel(emc, timing->emc_cfg_2, EMC_CFG_2); in tegra_emc_prepare_timing_change()
815 emc_seq_disable_auto_cal(emc); in tegra_emc_prepare_timing_change()
818 readl(emc->regs + EMC_INTSTATUS); in tegra_emc_prepare_timing_change()
823 static void tegra_emc_complete_timing_change(struct tegra_emc *emc, in tegra_emc_complete_timing_change() argument
826 struct emc_timing *timing = tegra_emc_find_timing(emc, rate); in tegra_emc_complete_timing_change()
827 struct emc_timing *last = &emc->last_timing; in tegra_emc_complete_timing_change()
834 emc_seq_wait_clkchange(emc); in tegra_emc_complete_timing_change()
839 emc->regs + EMC_AUTO_CAL_INTERVAL); in tegra_emc_complete_timing_change()
843 writel(timing->emc_cfg, emc->regs + EMC_CFG); in tegra_emc_complete_timing_change()
846 writel(timing->emc_zcal_cnt_long, emc->regs + EMC_ZCAL_WAIT_CNT); in tegra_emc_complete_timing_change()
849 if (emc->dram_type == DRAM_TYPE_LPDDR3 && in tegra_emc_complete_timing_change()
855 writel(val, emc->regs + EMC_BGBIAS_CTL0); in tegra_emc_complete_timing_change()
857 if (emc->dram_type == DRAM_TYPE_DDR3 && in tegra_emc_complete_timing_change()
858 readl(emc->regs + EMC_BGBIAS_CTL0) != in tegra_emc_complete_timing_change()
861 emc->regs + EMC_BGBIAS_CTL0); in tegra_emc_complete_timing_change()
865 emc->regs + EMC_AUTO_CAL_INTERVAL); in tegra_emc_complete_timing_change()
872 writel(timing->emc_sel_dpd_ctrl, emc->regs + EMC_SEL_DPD_CTRL); in tegra_emc_complete_timing_change()
873 emc_seq_update_timing(emc); in tegra_emc_complete_timing_change()
875 emc->last_timing = *timing; in tegra_emc_complete_timing_change()
880 static void emc_read_current_timing(struct tegra_emc *emc, in emc_read_current_timing() argument
887 readl(emc->regs + emc_burst_regs[i]); in emc_read_current_timing()
889 timing->emc_cfg = readl(emc->regs + EMC_CFG); in emc_read_current_timing()
899 static int emc_init(struct tegra_emc *emc) in emc_init() argument
901 emc->dram_type = readl(emc->regs + EMC_FBIO_CFG5); in emc_init()
903 if (emc->dram_type & EMC_FBIO_CFG5_DRAM_WIDTH_X64) in emc_init()
904 emc->dram_bus_width = 64; in emc_init()
906 emc->dram_bus_width = 32; in emc_init()
908 dev_info_once(emc->dev, "%ubit DRAM bus\n", emc->dram_bus_width); in emc_init()
910 emc->dram_type &= EMC_FBIO_CFG5_DRAM_TYPE_MASK; in emc_init()
911 emc->dram_type >>= EMC_FBIO_CFG5_DRAM_TYPE_SHIFT; in emc_init()
913 emc->dram_num = tegra_mc_get_emem_device_count(emc->mc); in emc_init()
915 emc_read_current_timing(emc, &emc->last_timing); in emc_init()
920 static int load_one_timing_from_dt(struct tegra_emc *emc, in load_one_timing_from_dt() argument
929 dev_err(emc->dev, "timing %pOFn: failed to read rate: %d\n", in load_one_timing_from_dt()
940 dev_err(emc->dev, in load_one_timing_from_dt()
949 dev_err(emc->dev, "timing %pOFn: failed to read " #prop ": %d\n", \ in load_one_timing_from_dt()
991 static int tegra_emc_load_timings_from_dt(struct tegra_emc *emc, in tegra_emc_load_timings_from_dt() argument
1000 emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing), in tegra_emc_load_timings_from_dt()
1002 if (!emc->timings) in tegra_emc_load_timings_from_dt()
1005 emc->num_timings = child_count; in tegra_emc_load_timings_from_dt()
1008 timing = &emc->timings[i++]; in tegra_emc_load_timings_from_dt()
1010 err = load_one_timing_from_dt(emc, timing, child); in tegra_emc_load_timings_from_dt()
1017 sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings, in tegra_emc_load_timings_from_dt()
1049 static void tegra_emc_rate_requests_init(struct tegra_emc *emc) in tegra_emc_rate_requests_init() argument
1054 emc->requested_rate[i].min_rate = 0; in tegra_emc_rate_requests_init()
1055 emc->requested_rate[i].max_rate = ULONG_MAX; in tegra_emc_rate_requests_init()
1059 static int emc_request_rate(struct tegra_emc *emc, in emc_request_rate() argument
1064 struct emc_rate_request *req = emc->requested_rate; in emc_request_rate()
1081 dev_err_ratelimited(emc->dev, "%s: type %u: out of range: %lu %lu\n", in emc_request_rate()
1090 err = dev_pm_opp_set_rate(emc->dev, min_rate); in emc_request_rate()
1094 emc->requested_rate[type].min_rate = new_min_rate; in emc_request_rate()
1095 emc->requested_rate[type].max_rate = new_max_rate; in emc_request_rate()
1100 static int emc_set_min_rate(struct tegra_emc *emc, unsigned long rate, in emc_set_min_rate() argument
1103 struct emc_rate_request *req = &emc->requested_rate[type]; in emc_set_min_rate()
1106 mutex_lock(&emc->rate_lock); in emc_set_min_rate()
1107 ret = emc_request_rate(emc, rate, req->max_rate, type); in emc_set_min_rate()
1108 mutex_unlock(&emc->rate_lock); in emc_set_min_rate()
1113 static int emc_set_max_rate(struct tegra_emc *emc, unsigned long rate, in emc_set_max_rate() argument
1116 struct emc_rate_request *req = &emc->requested_rate[type]; in emc_set_max_rate()
1119 mutex_lock(&emc->rate_lock); in emc_set_max_rate()
1120 ret = emc_request_rate(emc, req->min_rate, rate, type); in emc_set_max_rate()
1121 mutex_unlock(&emc->rate_lock); in emc_set_max_rate()
1151 static bool tegra_emc_validate_rate(struct tegra_emc *emc, unsigned long rate) in tegra_emc_validate_rate() argument
1155 for (i = 0; i < emc->num_timings; i++) in tegra_emc_validate_rate()
1156 if (rate == emc->timings[i].rate) in tegra_emc_validate_rate()
1165 struct tegra_emc *emc = s->private; in tegra_emc_debug_available_rates_show() local
1169 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_debug_available_rates_show()
1170 seq_printf(s, "%s%lu", prefix, emc->timings[i].rate); in tegra_emc_debug_available_rates_show()
1183 struct tegra_emc *emc = data; in tegra_emc_debug_min_rate_get() local
1185 *rate = emc->debugfs.min_rate; in tegra_emc_debug_min_rate_get()
1192 struct tegra_emc *emc = data; in tegra_emc_debug_min_rate_set() local
1195 if (!tegra_emc_validate_rate(emc, rate)) in tegra_emc_debug_min_rate_set()
1198 err = emc_set_min_rate(emc, rate, EMC_RATE_DEBUG); in tegra_emc_debug_min_rate_set()
1202 emc->debugfs.min_rate = rate; in tegra_emc_debug_min_rate_set()
1213 struct tegra_emc *emc = data; in tegra_emc_debug_max_rate_get() local
1215 *rate = emc->debugfs.max_rate; in tegra_emc_debug_max_rate_get()
1222 struct tegra_emc *emc = data; in tegra_emc_debug_max_rate_set() local
1225 if (!tegra_emc_validate_rate(emc, rate)) in tegra_emc_debug_max_rate_set()
1228 err = emc_set_max_rate(emc, rate, EMC_RATE_DEBUG); in tegra_emc_debug_max_rate_set()
1232 emc->debugfs.max_rate = rate; in tegra_emc_debug_max_rate_set()
1241 static void emc_debugfs_init(struct device *dev, struct tegra_emc *emc) in emc_debugfs_init() argument
1246 emc->debugfs.min_rate = ULONG_MAX; in emc_debugfs_init()
1247 emc->debugfs.max_rate = 0; in emc_debugfs_init()
1249 for (i = 0; i < emc->num_timings; i++) { in emc_debugfs_init()
1250 if (emc->timings[i].rate < emc->debugfs.min_rate) in emc_debugfs_init()
1251 emc->debugfs.min_rate = emc->timings[i].rate; in emc_debugfs_init()
1253 if (emc->timings[i].rate > emc->debugfs.max_rate) in emc_debugfs_init()
1254 emc->debugfs.max_rate = emc->timings[i].rate; in emc_debugfs_init()
1257 if (!emc->num_timings) { in emc_debugfs_init()
1258 emc->debugfs.min_rate = clk_get_rate(emc->clk); in emc_debugfs_init()
1259 emc->debugfs.max_rate = emc->debugfs.min_rate; in emc_debugfs_init()
1262 err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate, in emc_debugfs_init()
1263 emc->debugfs.max_rate); in emc_debugfs_init()
1266 emc->debugfs.min_rate, emc->debugfs.max_rate, in emc_debugfs_init()
1267 emc->clk); in emc_debugfs_init()
1271 emc->debugfs.root = debugfs_create_dir("emc", NULL); in emc_debugfs_init()
1273 debugfs_create_file("available_rates", 0444, emc->debugfs.root, emc, in emc_debugfs_init()
1275 debugfs_create_file("min_rate", 0644, emc->debugfs.root, in emc_debugfs_init()
1276 emc, &tegra_emc_debug_min_rate_fops); in emc_debugfs_init()
1277 debugfs_create_file("max_rate", 0644, emc->debugfs.root, in emc_debugfs_init()
1278 emc, &tegra_emc_debug_max_rate_fops); in emc_debugfs_init()
1318 struct tegra_emc *emc = to_tegra_emc_provider(dst->provider); in emc_icc_set() local
1331 dram_data_bus_width_bytes = emc->dram_bus_width / 8; in emc_icc_set()
1335 err = emc_set_min_rate(emc, rate, EMC_RATE_ICC); in emc_icc_set()
1342 static int tegra_emc_interconnect_init(struct tegra_emc *emc) in tegra_emc_interconnect_init() argument
1344 const struct tegra_mc_soc *soc = emc->mc->soc; in tegra_emc_interconnect_init()
1348 emc->provider.dev = emc->dev; in tegra_emc_interconnect_init()
1349 emc->provider.set = emc_icc_set; in tegra_emc_interconnect_init()
1350 emc->provider.data = &emc->provider; in tegra_emc_interconnect_init()
1351 emc->provider.aggregate = soc->icc_ops->aggregate; in tegra_emc_interconnect_init()
1352 emc->provider.xlate_extended = emc_of_icc_xlate_extended; in tegra_emc_interconnect_init()
1354 err = icc_provider_add(&emc->provider); in tegra_emc_interconnect_init()
1366 icc_node_add(node, &emc->provider); in tegra_emc_interconnect_init()
1381 icc_node_add(node, &emc->provider); in tegra_emc_interconnect_init()
1386 icc_nodes_remove(&emc->provider); in tegra_emc_interconnect_init()
1388 icc_provider_del(&emc->provider); in tegra_emc_interconnect_init()
1390 dev_err(emc->dev, "failed to initialize ICC: %d\n", err); in tegra_emc_interconnect_init()
1395 static int tegra_emc_opp_table_init(struct tegra_emc *emc) in tegra_emc_opp_table_init() argument
1400 err = dev_pm_opp_set_supported_hw(emc->dev, &hw_version, 1); in tegra_emc_opp_table_init()
1402 dev_err(emc->dev, "failed to set OPP supported HW: %d\n", err); in tegra_emc_opp_table_init()
1407 err = dev_pm_opp_of_add_table(emc->dev); in tegra_emc_opp_table_init()
1410 dev_err(emc->dev, "OPP table not found, please update your device tree\n"); in tegra_emc_opp_table_init()
1412 dev_err(emc->dev, "failed to add OPP table: %d\n", err); in tegra_emc_opp_table_init()
1417 dev_info_once(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n", in tegra_emc_opp_table_init()
1418 hw_version, clk_get_rate(emc->clk) / 1000000); in tegra_emc_opp_table_init()
1421 err = dev_pm_opp_set_rate(emc->dev, clk_get_rate(emc->clk)); in tegra_emc_opp_table_init()
1423 dev_err(emc->dev, "failed to initialize OPP clock: %d\n", err); in tegra_emc_opp_table_init()
1430 dev_pm_opp_of_remove_table(emc->dev); in tegra_emc_opp_table_init()
1445 struct tegra_emc *emc; in tegra_emc_probe() local
1449 emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL); in tegra_emc_probe()
1450 if (!emc) in tegra_emc_probe()
1453 mutex_init(&emc->rate_lock); in tegra_emc_probe()
1454 emc->dev = &pdev->dev; in tegra_emc_probe()
1456 emc->regs = devm_platform_ioremap_resource(pdev, 0); in tegra_emc_probe()
1457 if (IS_ERR(emc->regs)) in tegra_emc_probe()
1458 return PTR_ERR(emc->regs); in tegra_emc_probe()
1460 emc->mc = devm_tegra_memory_controller_get(&pdev->dev); in tegra_emc_probe()
1461 if (IS_ERR(emc->mc)) in tegra_emc_probe()
1462 return PTR_ERR(emc->mc); in tegra_emc_probe()
1468 err = tegra_emc_load_timings_from_dt(emc, np); in tegra_emc_probe()
1478 err = emc_init(emc); in tegra_emc_probe()
1484 platform_set_drvdata(pdev, emc); in tegra_emc_probe()
1494 emc->clk = devm_clk_get(&pdev->dev, "emc"); in tegra_emc_probe()
1495 if (IS_ERR(emc->clk)) { in tegra_emc_probe()
1496 err = PTR_ERR(emc->clk); in tegra_emc_probe()
1501 err = tegra_emc_opp_table_init(emc); in tegra_emc_probe()
1505 tegra_emc_rate_requests_init(emc); in tegra_emc_probe()
1508 emc_debugfs_init(&pdev->dev, emc); in tegra_emc_probe()
1510 tegra_emc_interconnect_init(emc); in tegra_emc_probe()