Lines Matching refs:sid
73 unsigned int sid) in tegra186_mc_client_sid_override() argument
77 value = readl(mc->regs + client->regs.sid.security); in tegra186_mc_client_sid_override()
96 writel(value, mc->regs + client->regs.sid.security); in tegra186_mc_client_sid_override()
99 value = readl(mc->regs + client->regs.sid.override); in tegra186_mc_client_sid_override()
102 if (old != sid) { in tegra186_mc_client_sid_override()
104 client->name, sid); in tegra186_mc_client_sid_override()
105 writel(sid, mc->regs + client->regs.sid.override); in tegra186_mc_client_sid_override()
124 u32 sid = fwspec->ids[0] & MC_SID_STREAMID_OVERRIDE_MASK; in tegra186_mc_probe_device() local
126 tegra186_mc_client_sid_override(mc, client, sid); in tegra186_mc_probe_device()
150 .sid = TEGRA186_SID_PASSTHROUGH,
152 .sid = {
160 .sid = TEGRA186_SID_AFI,
162 .sid = {
170 .sid = TEGRA186_SID_HDA,
172 .sid = {
180 .sid = TEGRA186_SID_HOST1X,
182 .sid = {
190 .sid = TEGRA186_SID_NVENC,
192 .sid = {
200 .sid = TEGRA186_SID_SATA,
202 .sid = {
210 .sid = TEGRA186_SID_PASSTHROUGH,
212 .sid = {
220 .sid = TEGRA186_SID_NVENC,
222 .sid = {
230 .sid = TEGRA186_SID_AFI,
232 .sid = {
240 .sid = TEGRA186_SID_HDA,
242 .sid = {
250 .sid = TEGRA186_SID_PASSTHROUGH,
252 .sid = {
260 .sid = TEGRA186_SID_SATA,
262 .sid = {
270 .sid = TEGRA186_SID_ISP,
272 .sid = {
280 .sid = TEGRA186_SID_ISP,
282 .sid = {
290 .sid = TEGRA186_SID_ISP,
292 .sid = {
300 .sid = TEGRA186_SID_XUSB_HOST,
302 .sid = {
310 .sid = TEGRA186_SID_XUSB_HOST,
312 .sid = {
320 .sid = TEGRA186_SID_XUSB_DEV,
322 .sid = {
330 .sid = TEGRA186_SID_XUSB_DEV,
332 .sid = {
340 .sid = TEGRA186_SID_TSEC,
342 .sid = {
350 .sid = TEGRA186_SID_TSEC,
352 .sid = {
360 .sid = TEGRA186_SID_GPU,
362 .sid = {
370 .sid = TEGRA186_SID_GPU,
372 .sid = {
380 .sid = TEGRA186_SID_SDMMC1,
382 .sid = {
390 .sid = TEGRA186_SID_SDMMC2,
392 .sid = {
400 .sid = TEGRA186_SID_SDMMC3,
402 .sid = {
410 .sid = TEGRA186_SID_SDMMC4,
412 .sid = {
420 .sid = TEGRA186_SID_SDMMC1,
422 .sid = {
430 .sid = TEGRA186_SID_SDMMC2,
432 .sid = {
440 .sid = TEGRA186_SID_SDMMC3,
442 .sid = {
450 .sid = TEGRA186_SID_SDMMC4,
452 .sid = {
460 .sid = TEGRA186_SID_VIC,
462 .sid = {
470 .sid = TEGRA186_SID_VIC,
472 .sid = {
480 .sid = TEGRA186_SID_VI,
482 .sid = {
490 .sid = TEGRA186_SID_NVDEC,
492 .sid = {
500 .sid = TEGRA186_SID_NVDEC,
502 .sid = {
510 .sid = TEGRA186_SID_APE,
512 .sid = {
520 .sid = TEGRA186_SID_APE,
522 .sid = {
530 .sid = TEGRA186_SID_NVJPG,
532 .sid = {
540 .sid = TEGRA186_SID_NVJPG,
542 .sid = {
550 .sid = TEGRA186_SID_SE,
552 .sid = {
560 .sid = TEGRA186_SID_SE,
562 .sid = {
570 .sid = TEGRA186_SID_ETR,
572 .sid = {
580 .sid = TEGRA186_SID_ETR,
582 .sid = {
590 .sid = TEGRA186_SID_TSECB,
592 .sid = {
600 .sid = TEGRA186_SID_TSECB,
602 .sid = {
610 .sid = TEGRA186_SID_GPU,
612 .sid = {
620 .sid = TEGRA186_SID_GPU,
622 .sid = {
630 .sid = TEGRA186_SID_GPCDMA_0,
632 .sid = {
640 .sid = TEGRA186_SID_GPCDMA_0,
642 .sid = {
650 .sid = TEGRA186_SID_EQOS,
652 .sid = {
660 .sid = TEGRA186_SID_EQOS,
662 .sid = {
670 .sid = TEGRA186_SID_UFSHC,
672 .sid = {
680 .sid = TEGRA186_SID_UFSHC,
682 .sid = {
690 .sid = TEGRA186_SID_NVDISPLAY,
692 .sid = {
700 .sid = TEGRA186_SID_BPMP,
702 .sid = {
710 .sid = TEGRA186_SID_BPMP,
712 .sid = {
720 .sid = TEGRA186_SID_BPMP,
722 .sid = {
730 .sid = TEGRA186_SID_BPMP,
732 .sid = {
740 .sid = TEGRA186_SID_AON,
742 .sid = {
750 .sid = TEGRA186_SID_AON,
752 .sid = {
760 .sid = TEGRA186_SID_AON,
762 .sid = {
770 .sid = TEGRA186_SID_AON,
772 .sid = {
780 .sid = TEGRA186_SID_SCE,
782 .sid = {
790 .sid = TEGRA186_SID_SCE,
792 .sid = {
800 .sid = TEGRA186_SID_SCE,
802 .sid = {
810 .sid = TEGRA186_SID_SCE,
812 .sid = {
820 .sid = TEGRA186_SID_APE,
822 .sid = {
830 .sid = TEGRA186_SID_APE,
832 .sid = {
840 .sid = TEGRA186_SID_NVDISPLAY,
842 .sid = {
850 .sid = TEGRA186_SID_VIC,
852 .sid = {
860 .sid = TEGRA186_SID_NVDEC,
862 .sid = {