Lines Matching defs:tegra210_emc_timing
802 struct tegra210_emc_timing { struct
803 u32 revision;
804 const char dvfs_ver[60];
805 u32 rate;
806 u32 min_volt;
807 u32 gpu_min_volt;
808 const char clock_src[32];
809 u32 clk_src_emc;
810 u32 needs_training;
811 u32 training_pattern;
812 u32 trained;
814 u32 periodic_training;
815 u32 trained_dram_clktree[DRAM_CLKTREE_NUM];
816 u32 current_dram_clktree[DRAM_CLKTREE_NUM];
817 u32 run_clocks;
818 u32 tree_margin;
820 u32 num_burst;
821 u32 num_burst_per_ch;
822 u32 num_trim;
823 u32 num_trim_per_ch;
824 u32 num_mc_regs;
825 u32 num_up_down;
826 u32 vref_num;
827 u32 training_mod_num;
828 u32 dram_timing_num;
830 u32 ptfv_list[PTFV_ARRAY_SIZE];
832 u32 burst_regs[BURST_REGS_SIZE];
833 u32 burst_reg_per_ch[BURST_REGS_PER_CHANNEL_SIZE];
834 u32 shadow_regs_ca_train[BURST_REGS_SIZE];
835 u32 shadow_regs_quse_train[BURST_REGS_SIZE];
836 u32 shadow_regs_rdwr_train[BURST_REGS_SIZE];
838 u32 trim_regs[TRIM_REGS_SIZE];
839 u32 trim_perch_regs[TRIM_REGS_PER_CHANNEL_SIZE];
841 u32 vref_perch_regs[VREF_REGS_PER_CHANNEL_SIZE];
843 u32 dram_timings[DRAM_TIMINGS_NUM];
844 u32 training_mod_regs[TRAINING_MOD_REGS_SIZE];
845 u32 save_restore_mod_regs[SAVE_RESTORE_MOD_REGS_SIZE];
846 u32 burst_mc_regs[BURST_MC_REGS_SIZE];
847 u32 la_scale_regs[BURST_UP_DOWN_REGS_SIZE];
849 u32 min_mrs_wait;
850 u32 emc_mrw;
851 u32 emc_mrw2;
852 u32 emc_mrw3;
853 u32 emc_mrw4;
854 u32 emc_mrw9;
855 u32 emc_mrs;
856 u32 emc_emrs;
857 u32 emc_emrs2;
858 u32 emc_auto_cal_config;
859 u32 emc_auto_cal_config2;
860 u32 emc_auto_cal_config3;
861 u32 emc_auto_cal_config4;
862 u32 emc_auto_cal_config5;
863 u32 emc_auto_cal_config6;
864 u32 emc_auto_cal_config7;
865 u32 emc_auto_cal_config8;
866 u32 emc_cfg_2;
867 u32 emc_sel_dpd_ctrl;
868 u32 emc_fdpd_ctrl_cmd_no_ramp;
892 struct tegra210_emc_timing *nominal; argument