Lines Matching refs:ldr
46 ldr r0, [r4, #EMIF_PM_BASE_ADDR_VIRT_OFFSET]
47 ldr r2, [r4, #EMIF_PM_REGS_VIRT_OFFSET]
50 ldr r1, [r0, #EMIF_SDRAM_CONFIG]
53 ldr r1, [r0, #EMIF_SDRAM_REFRESH_CONTROL]
56 ldr r1, [r0, #EMIF_SDRAM_TIMING_1]
59 ldr r1, [r0, #EMIF_SDRAM_TIMING_2]
62 ldr r1, [r0, #EMIF_SDRAM_TIMING_3]
65 ldr r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
68 ldr r1, [r0, #EMIF_POWER_MANAGEMENT_CTRL_SHDW]
71 ldr r1, [r0, #EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG]
74 ldr r1, [r0, #EMIF_DDR_PHY_CTRL_1]
77 ldr r1, [r0, #EMIF_COS_CONFIG]
80 ldr r1, [r0, #EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING]
83 ldr r1, [r0, #EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING]
86 ldr r1, [r0, #EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING]
89 ldr r1, [r0, #EMIF_OCP_CONFIG]
92 ldr r5, [r4, #EMIF_PM_CONFIG_OFFSET]
96 ldr r1, [r0, #EMIF_READ_WRITE_LEVELING_RAMP_CONTROL]
99 ldr r1, [r0, #EMIF_READ_WRITE_EXECUTION_THRESHOLD]
102 ldr r1, [r0, #EMIF_LPDDR2_NVM_TIMING]
105 ldr r1, [r0, #EMIF_LPDDR2_NVM_TIMING_SHDW]
108 ldr r1, [r0, #EMIF_DLL_CALIB_CTRL]
111 ldr r1, [r0, #EMIF_DLL_CALIB_CTRL_SHDW]
119 ldr r1, [r3, r5]
138 ldr r0, [r4, #EMIF_PM_BASE_ADDR_PHYS_OFFSET]
139 ldr r2, [r4, #EMIF_PM_REGS_PHYS_OFFSET]
142 ldr r1, [r2, #EMIF_DDR_PHY_CTLR_1_OFFSET]
146 ldr r1, [r2, #EMIF_TIMING1_VAL_OFFSET]
150 ldr r1, [r2, #EMIF_TIMING2_VAL_OFFSET]
154 ldr r1, [r2, #EMIF_TIMING3_VAL_OFFSET]
158 ldr r1, [r2, #EMIF_REF_CTRL_VAL_OFFSET]
162 ldr r1, [r2, #EMIF_PMCR_VAL_OFFSET]
165 ldr r1, [r2, #EMIF_PMCR_SHDW_VAL_OFFSET]
168 ldr r1, [r2, #EMIF_COS_CONFIG_OFFSET]
171 ldr r1, [r2, #EMIF_PRIORITY_TO_COS_MAPPING_OFFSET]
174 ldr r1, [r2, #EMIF_CONNECT_ID_SERV_1_MAP_OFFSET]
177 ldr r1, [r2, #EMIF_CONNECT_ID_SERV_2_MAP_OFFSET]
180 ldr r1, [r2, #EMIF_OCP_CONFIG_VAL_OFFSET]
183 ldr r5, [r4, #EMIF_PM_CONFIG_OFFSET]
187 ldr r1, [r2, #EMIF_RD_WR_LEVEL_RAMP_CTRL_OFFSET]
190 ldr r1, [r2, #EMIF_RD_WR_EXEC_THRESH_OFFSET]
193 ldr r1, [r2, #EMIF_LPDDR2_NVM_TIM_OFFSET]
196 ldr r1, [r2, #EMIF_LPDDR2_NVM_TIM_SHDW_OFFSET]
199 ldr r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_OFFSET]
202 ldr r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_SHDW_OFFSET]
205 ldr r1, [r2, #EMIF_ZQCFG_VAL_OFFSET]
216 ldr r1, [r3, r5]
229 ldr r1, [r2, #EMIF_ZQCFG_VAL_OFFSET]
233 ldr r1, [r2, #EMIF_SDCFG_VAL_OFFSET]
249 ldr r0, [r4, #EMIF_PM_BASE_ADDR_PHYS_OFFSET]
251 ldr r3, [r0, #EMIF_READ_WRITE_LEVELING_CONTROL]
253 ldr r2, [r0, #EMIF_SDRAM_CONFIG]
273 2: ldr r1, [r0, #EMIF_READ_WRITE_LEVELING_CONTROL]
292 ldr r0, [r4, #EMIF_PM_BASE_ADDR_VIRT_OFFSET]
293 ldr r2, [r4, #EMIF_PM_REGS_VIRT_OFFSET]
295 ldr r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
312 ldr r0, [r4, #EMIF_PM_BASE_ADDR_PHYS_OFFSET]
313 ldr r2, [r4, #EMIF_PM_REGS_PHYS_OFFSET]
323 ldr r1, [r2, #EMIF_PMCR_VAL_OFFSET]
331 1: ldr r1, [r0, #EMIF_STATUS]
349 ldr r0, [r4, #EMIF_PM_BASE_ADDR_VIRT_OFFSET]
350 ldr r2, [r4, #EMIF_PM_REGS_VIRT_OFFSET]
352 ldr r1, [r2, #EMIF_PMCR_VAL_OFFSET]
357 1: ldr r1, [r0, #EMIF_STATUS]