Lines Matching refs:dsisr
26 static irqreturn_t schedule_cxl_fault(struct cxl_context *ctx, u64 dsisr, u64 dar) in schedule_cxl_fault() argument
28 ctx->dsisr = dsisr; in schedule_cxl_fault()
36 u64 dsisr, dar; in cxl_irq_psl9() local
38 dsisr = irq_info->dsisr; in cxl_irq_psl9()
41 trace_cxl_psl9_irq(ctx, irq, dsisr, dar); in cxl_irq_psl9()
43 pr_devel("CXL interrupt %i for afu pe: %i DSISR: %#llx DAR: %#llx\n", irq, ctx->pe, dsisr, dar); in cxl_irq_psl9()
45 if (dsisr & CXL_PSL9_DSISR_An_TF) { in cxl_irq_psl9()
47 return schedule_cxl_fault(ctx, dsisr, dar); in cxl_irq_psl9()
50 if (dsisr & CXL_PSL9_DSISR_An_PE) in cxl_irq_psl9()
51 return cxl_ops->handle_psl_slice_error(ctx, dsisr, in cxl_irq_psl9()
53 if (dsisr & CXL_PSL9_DSISR_An_AE) { in cxl_irq_psl9()
78 if (dsisr & CXL_PSL9_DSISR_An_OC) in cxl_irq_psl9()
87 u64 dsisr, dar; in cxl_irq_psl8() local
89 dsisr = irq_info->dsisr; in cxl_irq_psl8()
92 trace_cxl_psl_irq(ctx, irq, dsisr, dar); in cxl_irq_psl8()
94 pr_devel("CXL interrupt %i for afu pe: %i DSISR: %#llx DAR: %#llx\n", irq, ctx->pe, dsisr, dar); in cxl_irq_psl8()
96 if (dsisr & CXL_PSL_DSISR_An_DS) { in cxl_irq_psl8()
108 return schedule_cxl_fault(ctx, dsisr, dar); in cxl_irq_psl8()
111 if (dsisr & CXL_PSL_DSISR_An_M) in cxl_irq_psl8()
113 if (dsisr & CXL_PSL_DSISR_An_P) in cxl_irq_psl8()
115 if (dsisr & CXL_PSL_DSISR_An_A) in cxl_irq_psl8()
117 if (dsisr & CXL_PSL_DSISR_An_S) in cxl_irq_psl8()
119 if (dsisr & CXL_PSL_DSISR_An_K) in cxl_irq_psl8()
122 if (dsisr & CXL_PSL_DSISR_An_DM) { in cxl_irq_psl8()
129 return schedule_cxl_fault(ctx, dsisr, dar); in cxl_irq_psl8()
131 if (dsisr & CXL_PSL_DSISR_An_ST) in cxl_irq_psl8()
133 if (dsisr & CXL_PSL_DSISR_An_UR) in cxl_irq_psl8()
135 if (dsisr & CXL_PSL_DSISR_An_PE) in cxl_irq_psl8()
136 return cxl_ops->handle_psl_slice_error(ctx, dsisr, in cxl_irq_psl8()
138 if (dsisr & CXL_PSL_DSISR_An_AE) { in cxl_irq_psl8()
164 if (dsisr & CXL_PSL_DSISR_An_OC) in cxl_irq_psl8()