Lines Matching refs:msm_host
139 #define msm_host_readl(msm_host, host, offset) \ argument
140 msm_host->var_ops->msm_readl_relaxed(host, offset)
142 #define msm_host_writel(msm_host, val, host, offset) \ argument
143 msm_host->var_ops->msm_writel_relaxed(val, host, offset)
295 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); in sdhci_priv_msm_offset() local
297 return msm_host->offset; in sdhci_priv_msm_offset()
308 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); in sdhci_msm_mci_variant_readl_relaxed() local
310 return readl_relaxed(msm_host->core_mem + offset); in sdhci_msm_mci_variant_readl_relaxed()
323 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); in sdhci_msm_mci_variant_writel_relaxed() local
325 writel_relaxed(val, msm_host->core_mem + offset); in sdhci_msm_mci_variant_writel_relaxed()
355 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); in msm_set_clock_rate_for_bus_mode() local
357 struct clk *core_clk = msm_host->bulk_clks[0].clk; in msm_set_clock_rate_for_bus_mode()
384 msm_host->clk_rate = desired_rate; in msm_set_clock_rate_for_bus_mode()
625 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); in msm_init_cm_dll() local
630 msm_host->offset; in msm_init_cm_dll()
632 if (msm_host->use_14lpp_dll_reset && !IS_ERR_OR_NULL(msm_host->xo_clk)) in msm_init_cm_dll()
633 xo_clk = clk_get_rate(msm_host->xo_clk); in msm_init_cm_dll()
646 if (msm_host->dll_config) in msm_init_cm_dll()
647 writel_relaxed(msm_host->dll_config, in msm_init_cm_dll()
650 if (msm_host->use_14lpp_dll_reset) { in msm_init_cm_dll()
676 if (!msm_host->dll_config) in msm_init_cm_dll()
679 if (msm_host->use_14lpp_dll_reset && in msm_init_cm_dll()
680 !IS_ERR_OR_NULL(msm_host->xo_clk)) { in msm_init_cm_dll()
716 if (msm_host->use_14lpp_dll_reset) { in msm_init_cm_dll()
717 if (!msm_host->dll_config) in msm_init_cm_dll()
730 if (msm_host->uses_tassadar_dll) { in msm_init_cm_dll()
739 if (msm_host->clk_rate < 150000000) in msm_init_cm_dll()
779 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); in msm_hc_select_default() local
782 msm_host->offset; in msm_hc_select_default()
784 if (!msm_host->use_cdclp533) { in msm_hc_select_default()
819 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); in msm_hc_select_hs400() local
824 msm_host->offset; in msm_hc_select_hs400()
836 if ((msm_host->tuning_done || ios.enhanced_strobe) && in msm_hc_select_hs400()
837 !msm_host->calibration_done) { in msm_hc_select_hs400()
845 if (!msm_host->clk_rate && !msm_host->use_cdclp533) { in msm_hc_select_hs400()
901 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); in sdhci_msm_cdclp533_calibration() local
905 msm_host->offset; in sdhci_msm_cdclp533_calibration()
918 ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase); in sdhci_msm_cdclp533_calibration()
1007 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); in sdhci_msm_cm_dll_sdc4_calibration() local
1020 if (msm_host->updated_ddr_cfg) in sdhci_msm_cm_dll_sdc4_calibration()
1024 writel_relaxed(msm_host->ddr_config, host->ioaddr + ddr_cfg_offset); in sdhci_msm_cm_dll_sdc4_calibration()
1058 if (!msm_host->use_14lpp_dll_reset) { in sdhci_msm_cm_dll_sdc4_calibration()
1080 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); in sdhci_msm_hs400_dll_calibration() local
1085 msm_host->offset; in sdhci_msm_hs400_dll_calibration()
1100 msm_host->saved_tuning_phase); in sdhci_msm_hs400_dll_calibration()
1110 if (msm_host->use_cdclp533) in sdhci_msm_hs400_dll_calibration()
1141 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); in sdhci_msm_restore_sdr_dll_config() local
1157 ret = msm_config_cm_dll_phase(host, msm_host->saved_tuning_phase); in sdhci_msm_restore_sdr_dll_config()
1191 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); in sdhci_msm_execute_tuning() local
1194 msm_host->use_cdr = false; in sdhci_msm_execute_tuning()
1200 msm_host->use_cdr = true; in sdhci_msm_execute_tuning()
1206 msm_host->tuning_done = 0; in sdhci_msm_execute_tuning()
1272 msm_host->saved_tuning_phase = phase; in sdhci_msm_execute_tuning()
1285 msm_host->tuning_done = true; in sdhci_msm_execute_tuning()
1298 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); in sdhci_msm_hs400() local
1302 (msm_host->tuning_done || ios->enhanced_strobe) && in sdhci_msm_hs400()
1303 !msm_host->calibration_done) { in sdhci_msm_hs400()
1306 msm_host->calibration_done = true; in sdhci_msm_hs400()
1318 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); in sdhci_msm_set_uhs_signaling() local
1322 msm_host->offset; in sdhci_msm_set_uhs_signaling()
1379 msm_host->calibration_done = false; in sdhci_msm_set_uhs_signaling()
1390 static int sdhci_msm_set_pincfg(struct sdhci_msm_host *msm_host, bool level) in sdhci_msm_set_pincfg() argument
1392 struct platform_device *pdev = msm_host->pdev; in sdhci_msm_set_pincfg()
1411 static int msm_toggle_vqmmc(struct sdhci_msm_host *msm_host, in msm_toggle_vqmmc() argument
1417 if (msm_host->vqmmc_enabled == level) in msm_toggle_vqmmc()
1422 if (msm_host->caps_0 & CORE_3_0V_SUPPORT) in msm_toggle_vqmmc()
1424 else if (msm_host->caps_0 & CORE_1_8V_SUPPORT) in msm_toggle_vqmmc()
1427 if (msm_host->caps_0 & CORE_VOLT_SUPPORT) { in msm_toggle_vqmmc()
1444 msm_host->vqmmc_enabled = level; in msm_toggle_vqmmc()
1449 static int msm_config_vqmmc_mode(struct sdhci_msm_host *msm_host, in msm_config_vqmmc_mode() argument
1462 static int sdhci_msm_set_vqmmc(struct sdhci_msm_host *msm_host, in sdhci_msm_set_vqmmc() argument
1485 ret = msm_config_vqmmc_mode(msm_host, mmc, level); in sdhci_msm_set_vqmmc()
1487 ret = msm_toggle_vqmmc(msm_host, mmc, level); in sdhci_msm_set_vqmmc()
1492 static inline void sdhci_msm_init_pwr_irq_wait(struct sdhci_msm_host *msm_host) in sdhci_msm_init_pwr_irq_wait() argument
1494 init_waitqueue_head(&msm_host->pwr_irq_wait); in sdhci_msm_init_pwr_irq_wait()
1498 struct sdhci_msm_host *msm_host) in sdhci_msm_complete_pwr_irq_wait() argument
1500 wake_up(&msm_host->pwr_irq_wait); in sdhci_msm_complete_pwr_irq_wait()
1515 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); in sdhci_msm_check_power_status() local
1519 msm_host->offset; in sdhci_msm_check_power_status()
1523 msm_host->curr_pwr_state, msm_host->curr_io_level); in sdhci_msm_check_power_status()
1531 if (!msm_host->mci_removed) in sdhci_msm_check_power_status()
1532 val = msm_host_readl(msm_host, host, in sdhci_msm_check_power_status()
1556 if ((req_type & msm_host->curr_pwr_state) || in sdhci_msm_check_power_status()
1557 (req_type & msm_host->curr_io_level)) in sdhci_msm_check_power_status()
1566 if (!wait_event_timeout(msm_host->pwr_irq_wait, in sdhci_msm_check_power_status()
1567 msm_host->pwr_irq_flag, in sdhci_msm_check_power_status()
1569 dev_warn(&msm_host->pdev->dev, in sdhci_msm_check_power_status()
1580 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); in sdhci_msm_dump_pwr_ctrl_regs() local
1582 msm_host->offset; in sdhci_msm_dump_pwr_ctrl_regs()
1586 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_status), in sdhci_msm_dump_pwr_ctrl_regs()
1587 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_mask), in sdhci_msm_dump_pwr_ctrl_regs()
1588 msm_host_readl(msm_host, host, msm_offset->core_pwrctl_ctl)); in sdhci_msm_dump_pwr_ctrl_regs()
1594 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); in sdhci_msm_handle_pwr_irq() local
1600 const struct sdhci_msm_offset *msm_offset = msm_host->offset; in sdhci_msm_handle_pwr_irq()
1602 irq_status = msm_host_readl(msm_host, host, in sdhci_msm_handle_pwr_irq()
1606 msm_host_writel(msm_host, irq_status, host, in sdhci_msm_handle_pwr_irq()
1616 while (irq_status & msm_host_readl(msm_host, host, in sdhci_msm_handle_pwr_irq()
1625 msm_host_writel(msm_host, irq_status, host, in sdhci_msm_handle_pwr_irq()
1644 ret = sdhci_msm_set_vqmmc(msm_host, mmc, in sdhci_msm_handle_pwr_irq()
1647 ret = sdhci_msm_set_pincfg(msm_host, in sdhci_msm_handle_pwr_irq()
1681 msm_host_writel(msm_host, irq_ack, host, in sdhci_msm_handle_pwr_irq()
1688 if (msm_host->caps_0 & CORE_VOLT_SUPPORT) { in sdhci_msm_handle_pwr_irq()
1706 (msm_host->caps_0 & CORE_3_0V_SUPPORT)) in sdhci_msm_handle_pwr_irq()
1709 (msm_host->caps_0 & CORE_1_8V_SUPPORT)) in sdhci_msm_handle_pwr_irq()
1718 msm_host->curr_pwr_state = pwr_state; in sdhci_msm_handle_pwr_irq()
1720 msm_host->curr_io_level = io_level; in sdhci_msm_handle_pwr_irq()
1723 mmc_hostname(msm_host->mmc), __func__, irq, irq_status, in sdhci_msm_handle_pwr_irq()
1731 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); in sdhci_msm_pwr_irq() local
1734 msm_host->pwr_irq_flag = 1; in sdhci_msm_pwr_irq()
1735 sdhci_msm_complete_pwr_irq_wait(msm_host); in sdhci_msm_pwr_irq()
1744 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); in sdhci_msm_get_max_clock() local
1745 struct clk *core_clk = msm_host->bulk_clks[0].clk; in sdhci_msm_get_max_clock()
1785 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); in sdhci_msm_set_clock() local
1788 host->mmc->actual_clock = msm_host->clk_rate = 0; in sdhci_msm_set_clock()
1828 static bool sdhci_msm_ice_supported(struct sdhci_msm_host *msm_host) in sdhci_msm_ice_supported() argument
1830 struct device *dev = mmc_dev(msm_host->mmc); in sdhci_msm_ice_supported()
1831 u32 regval = sdhci_msm_ice_readl(msm_host, QCOM_ICE_REG_VERSION); in sdhci_msm_ice_supported()
1847 regval = sdhci_msm_ice_readl(msm_host, QCOM_ICE_REG_FUSE_SETTING); in sdhci_msm_ice_supported()
1862 static int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host, in sdhci_msm_ice_init() argument
1865 struct mmc_host *mmc = msm_host->mmc; in sdhci_msm_ice_init()
1872 res = platform_get_resource_byname(msm_host->pdev, IORESOURCE_MEM, in sdhci_msm_ice_init()
1884 msm_host->ice_mem = devm_ioremap_resource(dev, res); in sdhci_msm_ice_init()
1885 if (IS_ERR(msm_host->ice_mem)) in sdhci_msm_ice_init()
1886 return PTR_ERR(msm_host->ice_mem); in sdhci_msm_ice_init()
1888 if (!sdhci_msm_ice_supported(msm_host)) in sdhci_msm_ice_init()
1899 static void sdhci_msm_ice_low_power_mode_enable(struct sdhci_msm_host *msm_host) in sdhci_msm_ice_low_power_mode_enable() argument
1903 regval = sdhci_msm_ice_readl(msm_host, QCOM_ICE_REG_ADVANCED_CONTROL); in sdhci_msm_ice_low_power_mode_enable()
1909 sdhci_msm_ice_writel(msm_host, regval, QCOM_ICE_REG_ADVANCED_CONTROL); in sdhci_msm_ice_low_power_mode_enable()
1912 static void sdhci_msm_ice_optimization_enable(struct sdhci_msm_host *msm_host) in sdhci_msm_ice_optimization_enable() argument
1917 regval = sdhci_msm_ice_readl(msm_host, QCOM_ICE_REG_ADVANCED_CONTROL); in sdhci_msm_ice_optimization_enable()
1921 sdhci_msm_ice_writel(msm_host, regval, QCOM_ICE_REG_ADVANCED_CONTROL); in sdhci_msm_ice_optimization_enable()
1937 static int sdhci_msm_ice_wait_bist_status(struct sdhci_msm_host *msm_host) in sdhci_msm_ice_wait_bist_status() argument
1942 err = readl_poll_timeout(msm_host->ice_mem + QCOM_ICE_REG_BIST_STATUS, in sdhci_msm_ice_wait_bist_status()
1946 dev_err(mmc_dev(msm_host->mmc), in sdhci_msm_ice_wait_bist_status()
1951 static void sdhci_msm_ice_enable(struct sdhci_msm_host *msm_host) in sdhci_msm_ice_enable() argument
1953 if (!(msm_host->mmc->caps2 & MMC_CAP2_CRYPTO)) in sdhci_msm_ice_enable()
1955 sdhci_msm_ice_low_power_mode_enable(msm_host); in sdhci_msm_ice_enable()
1956 sdhci_msm_ice_optimization_enable(msm_host); in sdhci_msm_ice_enable()
1957 sdhci_msm_ice_wait_bist_status(msm_host); in sdhci_msm_ice_enable()
1960 static int __maybe_unused sdhci_msm_ice_resume(struct sdhci_msm_host *msm_host) in sdhci_msm_ice_resume() argument
1962 if (!(msm_host->mmc->caps2 & MMC_CAP2_CRYPTO)) in sdhci_msm_ice_resume()
1964 return sdhci_msm_ice_wait_bist_status(msm_host); in sdhci_msm_ice_resume()
2018 static inline int sdhci_msm_ice_init(struct sdhci_msm_host *msm_host, in sdhci_msm_ice_init() argument
2024 static inline void sdhci_msm_ice_enable(struct sdhci_msm_host *msm_host) in sdhci_msm_ice_enable() argument
2029 sdhci_msm_ice_resume(struct sdhci_msm_host *msm_host) in sdhci_msm_ice_resume() argument
2057 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); in sdhci_msm_cqe_enable() local
2060 sdhci_msm_ice_enable(msm_host); in sdhci_msm_cqe_enable()
2123 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); in sdhci_msm_cqe_add_host() local
2147 msm_host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; in sdhci_msm_cqe_add_host()
2152 ret = sdhci_msm_ice_init(msm_host, cq_host); in sdhci_msm_cqe_add_host()
2200 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); in __sdhci_msm_check_write() local
2216 msm_host->transfer_mode = val; in __sdhci_msm_check_write()
2219 if (!msm_host->use_cdr) in __sdhci_msm_check_write()
2221 if ((msm_host->transfer_mode & SDHCI_TRNS_READ) && in __sdhci_msm_check_write()
2230 msm_host->pwr_irq_flag = 0; in __sdhci_msm_check_write()
2265 static void sdhci_msm_set_regulator_caps(struct sdhci_msm_host *msm_host) in sdhci_msm_set_regulator_caps() argument
2267 struct mmc_host *mmc = msm_host->mmc; in sdhci_msm_set_regulator_caps()
2271 const struct sdhci_msm_offset *msm_offset = msm_host->offset; in sdhci_msm_set_regulator_caps()
2289 u32 io_level = msm_host->curr_io_level; in sdhci_msm_set_regulator_caps()
2303 msm_host->caps_0 |= caps; in sdhci_msm_set_regulator_caps()
2307 static int sdhci_msm_register_vreg(struct sdhci_msm_host *msm_host) in sdhci_msm_register_vreg() argument
2311 ret = mmc_regulator_get_supply(msm_host->mmc); in sdhci_msm_register_vreg()
2315 sdhci_msm_set_regulator_caps(msm_host); in sdhci_msm_register_vreg()
2379 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); in sdhci_msm_dump_vendor_regs() local
2380 const struct sdhci_msm_offset *msm_offset = msm_host->offset; in sdhci_msm_dump_vendor_regs()
2475 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); in sdhci_msm_get_of_property() local
2478 &msm_host->ddr_config)) in sdhci_msm_get_of_property()
2479 msm_host->ddr_config = DDR_CONFIG_POR_VAL; in sdhci_msm_get_of_property()
2481 of_property_read_u32(node, "qcom,dll-config", &msm_host->dll_config); in sdhci_msm_get_of_property()
2526 struct sdhci_msm_host *msm_host; in sdhci_msm_probe() local
2536 host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host)); in sdhci_msm_probe()
2542 msm_host = sdhci_pltfm_priv(pltfm_host); in sdhci_msm_probe()
2543 msm_host->mmc = host->mmc; in sdhci_msm_probe()
2544 msm_host->pdev = pdev; in sdhci_msm_probe()
2556 msm_host->mci_removed = var_info->mci_removed; in sdhci_msm_probe()
2557 msm_host->restore_dll_config = var_info->restore_dll_config; in sdhci_msm_probe()
2558 msm_host->var_ops = var_info->var_ops; in sdhci_msm_probe()
2559 msm_host->offset = var_info->offset; in sdhci_msm_probe()
2561 msm_offset = msm_host->offset; in sdhci_msm_probe()
2566 msm_host->saved_tuning_phase = INVALID_TUNING_PHASE; in sdhci_msm_probe()
2573 msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus"); in sdhci_msm_probe()
2574 if (!IS_ERR(msm_host->bus_clk)) { in sdhci_msm_probe()
2576 ret = clk_set_rate(msm_host->bus_clk, INT_MAX); in sdhci_msm_probe()
2579 ret = clk_prepare_enable(msm_host->bus_clk); in sdhci_msm_probe()
2591 msm_host->bulk_clks[1].clk = clk; in sdhci_msm_probe()
2600 msm_host->bulk_clks[0].clk = clk; in sdhci_msm_probe()
2626 msm_host->bulk_clks[2].clk = clk; in sdhci_msm_probe()
2631 msm_host->bulk_clks[3].clk = clk; in sdhci_msm_probe()
2636 msm_host->bulk_clks[4].clk = clk; in sdhci_msm_probe()
2638 ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks), in sdhci_msm_probe()
2639 msm_host->bulk_clks); in sdhci_msm_probe()
2647 msm_host->xo_clk = devm_clk_get(&pdev->dev, "xo"); in sdhci_msm_probe()
2648 if (IS_ERR(msm_host->xo_clk)) { in sdhci_msm_probe()
2649 ret = PTR_ERR(msm_host->xo_clk); in sdhci_msm_probe()
2653 if (!msm_host->mci_removed) { in sdhci_msm_probe()
2654 msm_host->core_mem = devm_platform_ioremap_resource(pdev, 1); in sdhci_msm_probe()
2655 if (IS_ERR(msm_host->core_mem)) { in sdhci_msm_probe()
2656 ret = PTR_ERR(msm_host->core_mem); in sdhci_msm_probe()
2665 if (!msm_host->mci_removed) { in sdhci_msm_probe()
2667 msm_host_writel(msm_host, HC_MODE_EN, host, in sdhci_msm_probe()
2669 config = msm_host_readl(msm_host, host, in sdhci_msm_probe()
2672 msm_host_writel(msm_host, config, host, in sdhci_msm_probe()
2681 core_version = msm_host_readl(msm_host, host, in sdhci_msm_probe()
2690 msm_host->use_14lpp_dll_reset = true; in sdhci_msm_probe()
2697 msm_host->use_cdclp533 = true; in sdhci_msm_probe()
2711 msm_host->updated_ddr_cfg = true; in sdhci_msm_probe()
2714 msm_host->uses_tassadar_dll = true; in sdhci_msm_probe()
2716 ret = sdhci_msm_register_vreg(msm_host); in sdhci_msm_probe()
2736 msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq"); in sdhci_msm_probe()
2737 if (msm_host->pwr_irq < 0) { in sdhci_msm_probe()
2738 ret = msm_host->pwr_irq; in sdhci_msm_probe()
2742 sdhci_msm_init_pwr_irq_wait(msm_host); in sdhci_msm_probe()
2744 msm_host_writel(msm_host, INT_MASK, host, in sdhci_msm_probe()
2747 ret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL, in sdhci_msm_probe()
2755 msm_host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_NEED_RSP_BUSY; in sdhci_msm_probe()
2787 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks), in sdhci_msm_probe()
2788 msm_host->bulk_clks); in sdhci_msm_probe()
2790 if (!IS_ERR(msm_host->bus_clk)) in sdhci_msm_probe()
2791 clk_disable_unprepare(msm_host->bus_clk); in sdhci_msm_probe()
2801 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); in sdhci_msm_remove() local
2811 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks), in sdhci_msm_remove()
2812 msm_host->bulk_clks); in sdhci_msm_remove()
2813 if (!IS_ERR(msm_host->bus_clk)) in sdhci_msm_remove()
2814 clk_disable_unprepare(msm_host->bus_clk); in sdhci_msm_remove()
2823 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); in sdhci_msm_runtime_suspend() local
2827 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host->bulk_clks), in sdhci_msm_runtime_suspend()
2828 msm_host->bulk_clks); in sdhci_msm_runtime_suspend()
2837 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); in sdhci_msm_runtime_resume() local
2840 ret = clk_bulk_prepare_enable(ARRAY_SIZE(msm_host->bulk_clks), in sdhci_msm_runtime_resume()
2841 msm_host->bulk_clks); in sdhci_msm_runtime_resume()
2848 if (msm_host->restore_dll_config && msm_host->clk_rate) { in sdhci_msm_runtime_resume()
2854 dev_pm_opp_set_rate(dev, msm_host->clk_rate); in sdhci_msm_runtime_resume()
2856 return sdhci_msm_ice_resume(msm_host); in sdhci_msm_runtime_resume()