Lines Matching refs:caps2
459 struct cdns_nand_caps caps2; member
553 u8 data_dma_width = cdns_ctrl->caps2.data_dma_width; in cadence_nand_dma_buf_ok()
901 cdns_ctrl->caps2.max_banks = 1 << FIELD_GET(CTRL_FEATURES_N_BANKS, reg); in cadence_nand_get_caps()
904 cdns_ctrl->caps2.data_dma_width = 8; in cadence_nand_get_caps()
906 cdns_ctrl->caps2.data_dma_width = 4; in cadence_nand_get_caps()
909 cdns_ctrl->caps2.data_control_supp = true; in cadence_nand_get_caps()
913 cdns_ctrl->caps2.is_phy_type_dll = true; in cadence_nand_get_caps()
1188 if (cdns_ctrl->caps2.data_dma_width == 8) { in cadence_nand_hw_init()
1257 if (cdns_ctrl->caps2.data_control_supp) { in cadence_nand_prepare_data_size()
1328 if (cdns_ctrl->caps2.is_phy_type_dll) in cadence_nand_set_timings()
1333 if (cdns_ctrl->caps2.is_phy_type_dll) { in cadence_nand_set_timings()
1460 cdns_ctrl->caps2.data_control_supp) { in cadence_nand_write_page()
1639 cdns_ctrl->caps2.data_control_supp) { in cadence_nand_read_page()
1893 u8 data_dma_width = cdns_ctrl->caps2.data_dma_width; in cadence_nand_read_buf()
1966 u8 data_dma_width = cdns_ctrl->caps2.data_dma_width; in cadence_nand_write_buf()
2381 if (cdns_ctrl->caps2.is_phy_type_dll) in cadence_nand_setup_interface()
2568 if (cdns_ctrl->caps2.is_phy_type_dll) { in cadence_nand_setup_interface()
2603 if (!cdns_ctrl->caps2.is_phy_type_dll) in cadence_nand_setup_interface()
2616 if (cdns_ctrl->caps2.is_phy_type_dll) in cadence_nand_setup_interface()
2621 if (cdns_ctrl->caps2.is_phy_type_dll) { in cadence_nand_setup_interface()
2776 if (cs >= cdns_ctrl->caps2.max_banks) { in cadence_nand_chip_init()
2779 cs, cdns_ctrl->caps2.max_banks); in cadence_nand_chip_init()
2843 int max_cs = cdns_ctrl->caps2.max_banks; in cadence_nand_chips_init()