Lines Matching refs:REG_WR
225 REG_WR(bp, reg, val); in bnx2x_bits_en()
234 REG_WR(bp, reg, val); in bnx2x_bits_dis()
262 REG_WR(bp, params->lfa_base + in bnx2x_check_lfa()
381 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask); in bnx2x_get_epio()
403 REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output); in bnx2x_set_epio()
407 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask); in bnx2x_set_epio()
454 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688); in bnx2x_ets_e2e3a0_disabled()
463 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); in bnx2x_ets_e2e3a0_disabled()
465 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); in bnx2x_ets_e2e3a0_disabled()
469 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); in bnx2x_ets_e2e3a0_disabled()
473 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0); in bnx2x_ets_e2e3a0_disabled()
474 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0); in bnx2x_ets_e2e3a0_disabled()
475 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0); in bnx2x_ets_e2e3a0_disabled()
477 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0); in bnx2x_ets_e2e3a0_disabled()
478 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0); in bnx2x_ets_e2e3a0_disabled()
479 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0); in bnx2x_ets_e2e3a0_disabled()
481 REG_WR(bp, PBF_REG_ETS_ENABLED, 0); in bnx2x_ets_e2e3a0_disabled()
485 REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710); in bnx2x_ets_e2e3a0_disabled()
486 REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710); in bnx2x_ets_e2e3a0_disabled()
488 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680); in bnx2x_ets_e2e3a0_disabled()
489 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680); in bnx2x_ets_e2e3a0_disabled()
491 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); in bnx2x_ets_e2e3a0_disabled()
539 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 : in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
541 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 : in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
543 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 : in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
545 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 : in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
547 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 : in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
549 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 : in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
553 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6, in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
555 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7, in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
557 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8, in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
581 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210); in bnx2x_ets_e3b0_nig_disabled()
582 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0); in bnx2x_ets_e3b0_nig_disabled()
584 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210); in bnx2x_ets_e3b0_nig_disabled()
585 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8); in bnx2x_ets_e3b0_nig_disabled()
590 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS : in bnx2x_ets_e3b0_nig_disabled()
597 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543); in bnx2x_ets_e3b0_nig_disabled()
598 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0); in bnx2x_ets_e3b0_nig_disabled()
601 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB, in bnx2x_ets_e3b0_nig_disabled()
603 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5); in bnx2x_ets_e3b0_nig_disabled()
614 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f); in bnx2x_ets_e3b0_nig_disabled()
616 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff); in bnx2x_ets_e3b0_nig_disabled()
618 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : in bnx2x_ets_e3b0_nig_disabled()
627 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : in bnx2x_ets_e3b0_nig_disabled()
629 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : in bnx2x_ets_e3b0_nig_disabled()
631 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : in bnx2x_ets_e3b0_nig_disabled()
633 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 : in bnx2x_ets_e3b0_nig_disabled()
635 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 : in bnx2x_ets_e3b0_nig_disabled()
637 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 : in bnx2x_ets_e3b0_nig_disabled()
640 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0); in bnx2x_ets_e3b0_nig_disabled()
641 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0); in bnx2x_ets_e3b0_nig_disabled()
642 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0); in bnx2x_ets_e3b0_nig_disabled()
675 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound); in bnx2x_ets_e3b0_set_credit_upper_bound_pbf()
701 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688); in bnx2x_ets_e3b0_pbf_disabled()
704 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688); in bnx2x_ets_e3b0_pbf_disabled()
709 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688); in bnx2x_ets_e3b0_pbf_disabled()
712 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688); in bnx2x_ets_e3b0_pbf_disabled()
714 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 : in bnx2x_ets_e3b0_pbf_disabled()
718 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : in bnx2x_ets_e3b0_pbf_disabled()
721 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : in bnx2x_ets_e3b0_pbf_disabled()
735 REG_WR(bp, base_weight + (0x4 * i), 0); in bnx2x_ets_e3b0_pbf_disabled()
802 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT : in bnx2x_ets_e3b0_cli_map()
805 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : in bnx2x_ets_e3b0_cli_map()
808 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : in bnx2x_ets_e3b0_cli_map()
812 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : in bnx2x_ets_e3b0_cli_map()
881 REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig); in bnx2x_ets_e3b0_set_cos_bw()
883 REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf); in bnx2x_ets_e3b0_set_cos_bw()
1105 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1108 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf); in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1114 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1116 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1119 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf); in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1239 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18); in bnx2x_ets_bw_limit_common()
1246 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A); in bnx2x_ets_bw_limit_common()
1248 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, in bnx2x_ets_bw_limit_common()
1250 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, in bnx2x_ets_bw_limit_common()
1254 REG_WR(bp, PBF_REG_ETS_ENABLED, 1); in bnx2x_ets_bw_limit_common()
1257 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); in bnx2x_ets_bw_limit_common()
1265 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); in bnx2x_ets_bw_limit_common()
1268 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, in bnx2x_ets_bw_limit_common()
1270 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, in bnx2x_ets_bw_limit_common()
1299 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight); in bnx2x_ets_bw_limit()
1300 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight); in bnx2x_ets_bw_limit()
1302 REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight); in bnx2x_ets_bw_limit()
1303 REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight); in bnx2x_ets_bw_limit()
1320 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F); in bnx2x_ets_strict()
1324 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); in bnx2x_ets_strict()
1326 REG_WR(bp, PBF_REG_ETS_ENABLED, 0); in bnx2x_ets_strict()
1328 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100); in bnx2x_ets_strict()
1331 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos); in bnx2x_ets_strict()
1341 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val); in bnx2x_ets_strict()
1384 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); in bnx2x_update_pfc_xmac()
1385 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); in bnx2x_update_pfc_xmac()
1386 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); in bnx2x_update_pfc_xmac()
1392 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); in bnx2x_update_pfc_xmac()
1393 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); in bnx2x_update_pfc_xmac()
1394 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); in bnx2x_update_pfc_xmac()
1398 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO, in bnx2x_update_pfc_xmac()
1403 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI, in bnx2x_update_pfc_xmac()
1439 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode); in bnx2x_set_mdio_clk()
1477 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_emac_init()
1480 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in bnx2x_emac_init()
1518 REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN, in bnx2x_set_xumac_nig()
1520 REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN, in bnx2x_set_xumac_nig()
1522 REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN : in bnx2x_set_xumac_nig()
1542 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); in bnx2x_set_umac_rxtx()
1552 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_umac_enable()
1556 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in bnx2x_umac_enable()
1562 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); in bnx2x_umac_enable()
1595 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); in bnx2x_umac_enable()
1601 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, in bnx2x_umac_enable()
1603 REG_WR(bp, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11); in bnx2x_umac_enable()
1605 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0); in bnx2x_umac_enable()
1609 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0, in bnx2x_umac_enable()
1614 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1, in bnx2x_umac_enable()
1622 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); in bnx2x_umac_enable()
1631 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); in bnx2x_umac_enable()
1636 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); in bnx2x_umac_enable()
1667 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_xmac_init()
1671 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in bnx2x_xmac_init()
1677 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1); in bnx2x_xmac_init()
1680 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3); in bnx2x_xmac_init()
1683 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0); in bnx2x_xmac_init()
1688 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3); in bnx2x_xmac_init()
1693 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1); in bnx2x_xmac_init()
1697 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_xmac_init()
1701 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in bnx2x_xmac_init()
1720 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, in bnx2x_set_xmac_rxtx()
1722 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, in bnx2x_set_xmac_rxtx()
1730 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val); in bnx2x_set_xmac_rxtx()
1752 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0); in bnx2x_xmac_enable()
1758 REG_WR(bp, xmac_base + XMAC_REG_RX_LSS_CTRL, in bnx2x_xmac_enable()
1761 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); in bnx2x_xmac_enable()
1762 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, in bnx2x_xmac_enable()
1767 REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710); in bnx2x_xmac_enable()
1770 REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800); in bnx2x_xmac_enable()
1777 REG_WR(bp, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008); in bnx2x_xmac_enable()
1778 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x1); in bnx2x_xmac_enable()
1780 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x0); in bnx2x_xmac_enable()
1795 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val); in bnx2x_xmac_enable()
1815 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_emac_enable()
1819 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1); in bnx2x_emac_enable()
1829 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane); in bnx2x_emac_enable()
1831 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); in bnx2x_emac_enable()
1836 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0); in bnx2x_emac_enable()
1905 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1); in bnx2x_emac_enable()
1913 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1); in bnx2x_emac_enable()
1916 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0); in bnx2x_emac_enable()
1917 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0); in bnx2x_emac_enable()
1918 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0); in bnx2x_emac_enable()
1921 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1); in bnx2x_emac_enable()
1928 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val); in bnx2x_emac_enable()
1929 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1); in bnx2x_emac_enable()
1931 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0); in bnx2x_emac_enable()
2095 REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask); in bnx2x_pfc_nig_rx_priority_mask()
2103 REG_WR(bp, params->shmem_base + in bnx2x_update_mng()
2113 REG_WR(bp, params->shmem2_base + in bnx2x_update_link_attr()
2167 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN : in bnx2x_update_pfc_nig()
2169 REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 : in bnx2x_update_pfc_nig()
2171 REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 : in bnx2x_update_pfc_nig()
2173 REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 : in bnx2x_update_pfc_nig()
2176 REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 : in bnx2x_update_pfc_nig()
2179 REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK : in bnx2x_update_pfc_nig()
2182 REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 : in bnx2x_update_pfc_nig()
2186 REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN : in bnx2x_update_pfc_nig()
2190 REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE : in bnx2x_update_pfc_nig()
2201 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 : in bnx2x_update_pfc_nig()
2205 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 : in bnx2x_update_pfc_nig()
2209 REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS : in bnx2x_update_pfc_nig()
2263 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val); in bnx2x_update_pfc()
2407 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_bmac_enable()
2412 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in bnx2x_bmac_enable()
2416 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1); in bnx2x_bmac_enable()
2423 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1); in bnx2x_bmac_enable()
2424 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0); in bnx2x_bmac_enable()
2425 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0); in bnx2x_bmac_enable()
2431 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val); in bnx2x_bmac_enable()
2432 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0); in bnx2x_bmac_enable()
2433 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0); in bnx2x_bmac_enable()
2434 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0); in bnx2x_bmac_enable()
2435 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1); in bnx2x_bmac_enable()
2436 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1); in bnx2x_bmac_enable()
2477 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1); in bnx2x_pbf_update()
2501 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1); in bnx2x_pbf_update()
2503 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0); in bnx2x_pbf_update()
2510 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); in bnx2x_pbf_update()
2512 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh); in bnx2x_pbf_update()
2524 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd); in bnx2x_pbf_update()
2529 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1); in bnx2x_pbf_update()
2531 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0); in bnx2x_pbf_update()
2534 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0); in bnx2x_pbf_update()
2597 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, in bnx2x_cl22_write()
2604 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); in bnx2x_cl22_write()
2619 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); in bnx2x_cl22_write()
2633 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, in bnx2x_cl22_read()
2640 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); in bnx2x_cl22_read()
2658 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); in bnx2x_cl22_read()
2685 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); in bnx2x_cl45_read()
2706 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); in bnx2x_cl45_read()
2761 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); in bnx2x_cl45_write()
2781 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); in bnx2x_cl45_write()
2908 REG_WR(bp, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2), in bnx2x_eee_set_timers()
2958 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0); in bnx2x_eee_disable()
2975 REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20); in bnx2x_eee_advertise()
2999 REG_WR(bp, params->shmem2_base + in bnx2x_update_mng_eee()
3104 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); in bnx2x_bsc_read()
3108 REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val); in bnx2x_bsc_read()
3115 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); in bnx2x_bsc_read()
3140 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); in bnx2x_bsc_read()
3317 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1); in bnx2x_set_serdes_access()
3318 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000); in bnx2x_set_serdes_access()
3320 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f); in bnx2x_set_serdes_access()
3323 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0); in bnx2x_set_serdes_access()
3335 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); in bnx2x_serdes_deassert()
3337 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); in bnx2x_serdes_deassert()
3341 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10, in bnx2x_serdes_deassert()
3353 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0); in bnx2x_xgxs_specific_func()
3354 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18, in bnx2x_xgxs_specific_func()
3371 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); in bnx2x_xgxs_deassert()
3373 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); in bnx2x_xgxs_deassert()
6118 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8, in bnx2x_rearm_latch_signal()
6259 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, in bnx2x_set_xgxs_loopback()
6280 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, in bnx2x_set_xgxs_loopback()
6322 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0); in bnx2x_set_led()
6323 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, in bnx2x_set_led()
6354 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); in bnx2x_set_led()
6355 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); in bnx2x_set_led()
6375 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); in bnx2x_set_led()
6380 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); in bnx2x_set_led()
6382 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, in bnx2x_set_led()
6387 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); in bnx2x_set_led()
6401 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, in bnx2x_set_led()
6405 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0); in bnx2x_set_led()
6408 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, in bnx2x_set_led()
6411 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, in bnx2x_set_led()
6413 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + in bnx2x_set_led()
6425 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 in bnx2x_set_led()
6427 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 + in bnx2x_set_led()
6429 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 + in bnx2x_set_led()
6610 REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, in bnx2x_int_link_reset()
6651 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); in bnx2x_update_link_down()
6655 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); in bnx2x_update_link_down()
6665 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), in bnx2x_update_link_down()
6667 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2), in bnx2x_update_link_down()
6716 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + in bnx2x_update_link_up()
6718 REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 1); in bnx2x_update_link_up()
6719 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + in bnx2x_update_link_up()
6755 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0); in bnx2x_update_link_up()
6786 REG_WR(bp, addr, val); in bnx2x_chng_link_count()
6848 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); in bnx2x_link_update()
6990 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, in bnx2x_link_update()
7077 REG_WR(bp, ver_addr, spirom_ver); in bnx2x_save_spirom_version()
8237 REG_WR(bp, sync_offset, media_types); in bnx2x_get_edc_mode()
8598 REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e); in bnx2x_warpcore_hw_reset()
8601 REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1); in bnx2x_warpcore_hw_reset()
8602 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0); in bnx2x_warpcore_hw_reset()
8603 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0); in bnx2x_warpcore_hw_reset()
11441 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); in bnx2x_54618se_config_loopback()
11446 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); in bnx2x_54618se_config_loopback()
12652 REG_WR(bp, sync_offset, media_types); in bnx2x_phy_probe()
12679 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0); in bnx2x_init_bmac_loopback()
12698 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0); in bnx2x_init_emac_loopback()
12724 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_init_xmac_loopback()
12739 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_init_umac_loopback()
12789 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_init_xgxs_loopback()
12802 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val); in bnx2x_set_rx_filter()
12805 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4, in bnx2x_set_rx_filter()
12809 REG_WR(bp, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP : in bnx2x_set_rx_filter()
12848 REG_WR(bp, GRCBASE_MISC + in bnx2x_avoid_link_flap()
12852 REG_WR(bp, GRCBASE_MISC + in bnx2x_avoid_link_flap()
12876 REG_WR(bp, params->lfa_base + in bnx2x_avoid_link_flap()
12880 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_avoid_link_flap()
12899 REG_WR(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12903 REG_WR(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12907 REG_WR(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12912 REG_WR(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12923 REG_WR(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12942 REG_WR(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
13056 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); in bnx2x_link_reset()
13060 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0); in bnx2x_link_reset()
13061 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0); in bnx2x_link_reset()
13072 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); in bnx2x_link_reset()
13111 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_link_reset()
13113 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0); in bnx2x_link_reset()
13114 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0); in bnx2x_link_reset()
13120 REG_WR(bp, xmac_base + XMAC_REG_CTRL, in bnx2x_link_reset()
13140 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); in bnx2x_lfa_reset()
13175 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_lfa_reset()
13321 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); in bnx2x_8726_common_init_phy()
13587 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1); in bnx2x_common_init_phy()
13690 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); in bnx2x_analyze_link_error()
13703 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_analyze_link_error()
13752 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); in bnx2x_check_half_open_conn()
13753 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, in bnx2x_check_half_open_conn()
14046 REG_WR(bp, sync_offset, vars->aeu_int_mask); in bnx2x_init_mod_abs_int()
14059 REG_WR(bp, offset, aeu_mask); in bnx2x_init_mod_abs_int()
14064 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); in bnx2x_init_mod_abs_int()