Lines Matching refs:phy_index

1446 	u8 phy_index;  in bnx2x_set_mdio_emac_per_phy()  local
1448 	for (phy_index = INT_PHY; phy_index < params->num_phys;  in bnx2x_set_mdio_emac_per_phy()
1449 	      phy_index++)  in bnx2x_set_mdio_emac_per_phy()
1451 				   params->phy[phy_index].mdio_ctrl);  in bnx2x_set_mdio_emac_per_phy()
3191 	u8 phy_index;  in bnx2x_phy_read()  local
3195 	for (phy_index = 0; phy_index < params->num_phys; phy_index++) {  in bnx2x_phy_read()
3196 		if (params->phy[phy_index].addr == phy_addr) {  in bnx2x_phy_read()
3198 					       &params->phy[phy_index], devad,  in bnx2x_phy_read()
3208 	u8 phy_index;  in bnx2x_phy_write()  local
3212 	for (phy_index = 0; phy_index < params->num_phys; phy_index++) {  in bnx2x_phy_write()
3213 		if (params->phy[phy_index].addr == phy_addr) {  in bnx2x_phy_write()
3215 						&params->phy[phy_index], devad,  in bnx2x_phy_write()
3423 	u8 actual_phy_idx, phy_index, link_cfg_idx;  in set_phy_vars()  local
3426 	for (phy_index = INT_PHY; phy_index < params->num_phys;  in set_phy_vars()
3427 	      phy_index++) {  in set_phy_vars()
3428 		link_cfg_idx = LINK_CONFIG_IDX(phy_index);  in set_phy_vars()
3429 		actual_phy_idx = phy_index;  in set_phy_vars()
3431 			if (phy_index == EXT_PHY1)  in set_phy_vars()
3433 			else if (phy_index == EXT_PHY2)  in set_phy_vars()
6451 	u16 gp_status = 0, phy_index = 0;  in bnx2x_test_link()  local
6501 		for (phy_index = EXT_PHY1; phy_index < params->num_phys;  in bnx2x_test_link()
6502 		      phy_index++) {  in bnx2x_test_link()
6503 			serdes_phy_type = ((params->phy[phy_index].media_type ==  in bnx2x_test_link()
6505 					   (params->phy[phy_index].media_type ==  in bnx2x_test_link()
6507 					   (params->phy[phy_index].media_type ==  in bnx2x_test_link()
6509 					   (params->phy[phy_index].media_type ==  in bnx2x_test_link()
6514 			if (params->phy[phy_index].read_status) {  in bnx2x_test_link()
6516 					params->phy[phy_index].read_status(  in bnx2x_test_link()
6517 						&params->phy[phy_index],  in bnx2x_test_link()
6531 	u8 phy_index, non_ext_phy;  in bnx2x_link_initialize()  local
6573 		for (phy_index = EXT_PHY1; phy_index < params->num_phys;  in bnx2x_link_initialize()
6574 		      phy_index++) {  in bnx2x_link_initialize()
6580 			if (params->phy[phy_index].supported &  in bnx2x_link_initialize()
6584 			if (phy_index == EXT_PHY2 &&  in bnx2x_link_initialize()
6591 			params->phy[phy_index].config_init(  in bnx2x_link_initialize()
6592 				&params->phy[phy_index],  in bnx2x_link_initialize()
6806 	u8 link_10g_plus, phy_index;  in bnx2x_link_update()  local
6815 	for (phy_index = INT_PHY; phy_index < params->num_phys;  in bnx2x_link_update()
6816 	      phy_index++) {  in bnx2x_link_update()
6817 		phy_vars[phy_index].flow_ctrl = 0;  in bnx2x_link_update()
6818 		phy_vars[phy_index].link_status = 0;  in bnx2x_link_update()
6819 		phy_vars[phy_index].line_speed = 0;  in bnx2x_link_update()
6820 		phy_vars[phy_index].duplex = DUPLEX_FULL;  in bnx2x_link_update()
6821 		phy_vars[phy_index].phy_link_up = 0;  in bnx2x_link_update()
6822 		phy_vars[phy_index].link_up = 0;  in bnx2x_link_update()
6823 		phy_vars[phy_index].fault_detected = 0;  in bnx2x_link_update()
6825 		phy_vars[phy_index].eee_status = vars->eee_status;  in bnx2x_link_update()
6857 	for (phy_index = EXT_PHY1; phy_index < params->num_phys;  in bnx2x_link_update()
6858 	      phy_index++) {  in bnx2x_link_update()
6859 		struct bnx2x_phy *phy = &params->phy[phy_index];  in bnx2x_link_update()
6864 					       &phy_vars[phy_index]);  in bnx2x_link_update()
6867 				   phy_index);  in bnx2x_link_update()
6870 				   phy_index);  in bnx2x_link_update()
6876 			active_external_phy = phy_index;  in bnx2x_link_update()
6963 	for (phy_index = EXT_PHY1; phy_index < params->num_phys;  in bnx2x_link_update()
6964 	      phy_index++) {  in bnx2x_link_update()
6965 		if (params->phy[phy_index].flags &  in bnx2x_link_update()
6968 						 phy_index ==  in bnx2x_link_update()
12148 				     u8 phy_index)  in bnx2x_populate_preemphasis()  argument
12157 		if (phy_index == INT_PHY || phy_index == EXT_PHY1) {  in bnx2x_populate_preemphasis()
12184 				    u8 phy_index, u8 port)  in bnx2x_get_ext_phy_config()  argument
12187 	switch (phy_index) {  in bnx2x_get_ext_phy_config()
12199 		DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);  in bnx2x_get_ext_phy_config()
12343 				  u8 phy_index,  in bnx2x_populate_ext_phy()  argument
12352 						  phy_index, port);  in bnx2x_populate_ext_phy()
12418 	bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);  in bnx2x_populate_ext_phy()
12426 	if (phy_index == EXT_PHY1) {  in bnx2x_populate_ext_phy()
12464 		   phy_type, port, phy_index);  in bnx2x_populate_ext_phy()
12470 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,  in bnx2x_populate_phy()  argument
12474 	if (phy_index == INT_PHY)  in bnx2x_populate_phy()
12477 	return bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,  in bnx2x_populate_phy()
12483 			      u8 phy_index)  in bnx2x_phy_def_cfg()  argument
12488 	if (phy_index == EXT_PHY2) {  in bnx2x_phy_def_cfg()
12507 	   phy_index, link_config, phy->speed_cap_mask);  in bnx2x_phy_def_cfg()
12590 	u8 phy_index, actual_phy_idx;  in bnx2x_phy_probe()  local
12599 	for (phy_index = INT_PHY; phy_index < MAX_PHYS;  in bnx2x_phy_probe()
12600 	      phy_index++) {  in bnx2x_phy_probe()
12601 		actual_phy_idx = phy_index;  in bnx2x_phy_probe()
12603 			if (phy_index == EXT_PHY1)  in bnx2x_phy_probe()
12605 			else if (phy_index == EXT_PHY2)  in bnx2x_phy_probe()
12610 			   phy_index, actual_phy_idx);  in bnx2x_phy_probe()
12612 		if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,  in bnx2x_phy_probe()
12617 				   phy_index);  in bnx2x_phy_probe()
12618 			for (phy_index = INT_PHY;  in bnx2x_phy_probe()
12619 			      phy_index < MAX_PHYS;  in bnx2x_phy_probe()
12620 			      phy_index++)  in bnx2x_phy_probe()
12654 		bnx2x_phy_def_cfg(params, phy, phy_index);  in bnx2x_phy_probe()
12781 		u8 phy_index;  in bnx2x_init_xgxs_loopback()  local
12782 		for (phy_index = EXT_PHY1;  in bnx2x_init_xgxs_loopback()
12783 		      phy_index < params->num_phys; phy_index++)  in bnx2x_init_xgxs_loopback()
12784 			if (params->phy[phy_index].config_loopback)  in bnx2x_init_xgxs_loopback()
12785 				params->phy[phy_index].config_loopback(  in bnx2x_init_xgxs_loopback()
12786 					&params->phy[phy_index],  in bnx2x_init_xgxs_loopback()
13040 	u8 phy_index, port = params->port, clear_latch_ind = 0;  in bnx2x_link_reset()  local
13083 		for (phy_index = EXT_PHY1; phy_index < params->num_phys;  in bnx2x_link_reset()
13084 		      phy_index++) {  in bnx2x_link_reset()
13085 			if (params->phy[phy_index].link_reset) {  in bnx2x_link_reset()
13087 						  &params->phy[phy_index]);  in bnx2x_link_reset()
13088 				params->phy[phy_index].link_reset(  in bnx2x_link_reset()
13089 					&params->phy[phy_index],  in bnx2x_link_reset()
13092 			if (params->phy[phy_index].flags &  in bnx2x_link_reset()
13184 				      u32 shmem2_base_path[], u8 phy_index,  in bnx2x_8073_common_init_phy()  argument
13212 		if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,  in bnx2x_8073_common_init_phy()
13310 				      u32 shmem2_base_path[], u8 phy_index,  in bnx2x_8726_common_init_phy()  argument
13337 		if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,  in bnx2x_8726_common_init_phy()
13405 				      u32 shmem2_base_path[], u8 phy_index,  in bnx2x_8727_common_init_phy()  argument
13453 		if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,  in bnx2x_8727_common_init_phy()
13505 						u8 phy_index,  in bnx2x_84833_common_init_phy()  argument
13519 				     u32 shmem2_base_path[], u8 phy_index,  in bnx2x_ext_phy_common_init()  argument
13528 						phy_index, chip_id);  in bnx2x_ext_phy_common_init()
13535 						phy_index, chip_id);  in bnx2x_ext_phy_common_init()
13544 						phy_index, chip_id);  in bnx2x_ext_phy_common_init()
13554 						phy_index, chip_id);  in bnx2x_ext_phy_common_init()
13578 	u8 phy_index = 0;  in bnx2x_common_init_phy()  local
13600 	for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;  in bnx2x_common_init_phy()
13601 	      phy_index++) {  in bnx2x_common_init_phy()
13604 							  phy_index, 0);  in bnx2x_common_init_phy()
13608 						phy_index, ext_phy_type,  in bnx2x_common_init_phy()
13960 	u8 phy_index, fan_failure_det_req = 0;  in bnx2x_fan_failure_det_req()  local
13962 	for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;  in bnx2x_fan_failure_det_req()
13963 	      phy_index++) {  in bnx2x_fan_failure_det_req()
13964 		if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,  in bnx2x_fan_failure_det_req()
13978 	u8 phy_index;  in bnx2x_hw_reset_phy()  local
13987 	for (phy_index = INT_PHY; phy_index < MAX_PHYS;  in bnx2x_hw_reset_phy()
13988 	      phy_index++) {  in bnx2x_hw_reset_phy()
13989 		if (params->phy[phy_index].hw_reset) {  in bnx2x_hw_reset_phy()
13990 			params->phy[phy_index].hw_reset(  in bnx2x_hw_reset_phy()
13991 				&params->phy[phy_index],  in bnx2x_hw_reset_phy()
13993 			params->phy[phy_index] = phy_null;  in bnx2x_hw_reset_phy()
14002 	u8 gpio_num = 0xff, gpio_port = 0xff, phy_index;  in bnx2x_init_mod_abs_int()  local
14014 		for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;  in bnx2x_init_mod_abs_int()
14015 		      phy_index++) {  in bnx2x_init_mod_abs_int()
14016 			if (bnx2x_populate_phy(bp, phy_index, shmem_base,  in bnx2x_init_mod_abs_int()