Lines Matching defs:fman_qmi_regs
386 struct fman_qmi_regs { struct
387 u32 fmqm_gc; /* General Configuration Register 0x00 */
388 u32 res0004; /* 0x04 */
389 u32 fmqm_eie; /* Error Interrupt Event Register 0x08 */
390 u32 fmqm_eien; /* Error Interrupt Enable Register 0x0c */
391 u32 fmqm_eif; /* Error Interrupt Force Register 0x10 */
392 u32 fmqm_ie; /* Interrupt Event Register 0x14 */
393 u32 fmqm_ien; /* Interrupt Enable Register 0x18 */
394 u32 fmqm_if; /* Interrupt Force Register 0x1c */
395 u32 fmqm_gs; /* Global Status Register 0x20 */
396 u32 fmqm_ts; /* Task Status Register 0x24 */
397 u32 fmqm_etfc; /* Enqueue Total Frame Counter 0x28 */
398 u32 fmqm_dtfc; /* Dequeue Total Frame Counter 0x2c */
399 u32 fmqm_dc0; /* Dequeue Counter 0 0x30 */
400 u32 fmqm_dc1; /* Dequeue Counter 1 0x34 */
401 u32 fmqm_dc2; /* Dequeue Counter 2 0x38 */
402 u32 fmqm_dc3; /* Dequeue Counter 3 0x3c */
403 u32 fmqm_dfdc; /* Dequeue FQID from Default Counter 0x40 */
404 u32 fmqm_dfcc; /* Dequeue FQID from Context Counter 0x44 */
405 u32 fmqm_dffc; /* Dequeue FQID from FD Counter 0x48 */
406 u32 fmqm_dcc; /* Dequeue Confirm Counter 0x4c */
407 u32 res0050[7]; /* 0x50 - 0x6b */
408 u32 fmqm_tapc; /* Tnum Aging Period Control 0x6c */
409 u32 fmqm_dmcvc; /* Dequeue MAC Command Valid Counter 0x70 */
410 u32 fmqm_difdcc; /* Dequeue Invalid FD Command Counter 0x74 */
411 u32 fmqm_da1v; /* Dequeue A1 Valid Counter 0x78 */
412 u32 res007c; /* 0x7c */
413 u32 fmqm_dtc; /* 0x80 Debug Trap Counter 0x80 */
414 u32 fmqm_efddd; /* 0x84 Enqueue Frame desc Dynamic dbg 0x84 */
415 u32 res0088[2]; /* 0x88 - 0x8f */
416 struct {
425 } dbg_traps[3]; /* 0x90 - 0xef */
426 u8 res00f0[0x400 - 0xf0]; /* 0xf0 - 0x3ff */