Lines Matching refs:wr32
75 wr32(&pf->hw, GLINT_DYN_CTL(i), GLINT_DYN_CTL_CLEARPBA_M); in ice_free_vf_res()
101 wr32(hw, VPINT_ALLOC(vf->vf_id), 0); in ice_dis_vf_mappings()
102 wr32(hw, VPINT_ALLOC_PCI(vf->vf_id), 0); in ice_dis_vf_mappings()
113 wr32(hw, GLINT_VECT2FUNC(v), reg); in ice_dis_vf_mappings()
117 wr32(hw, VPLAN_TX_QBASE(vf->vf_id), 0); in ice_dis_vf_mappings()
122 wr32(hw, VPLAN_RX_QBASE(vf->vf_id), 0); in ice_dis_vf_mappings()
203 wr32(hw, GLGEN_VFLRSTAT(reg_idx), BIT(bit_idx)); in ice_free_vfs()
307 wr32(hw, VPINT_ALLOC(vf->vf_id), reg); in ice_ena_vf_msix_mappings()
313 wr32(hw, VPINT_ALLOC_PCI(vf->vf_id), reg); in ice_ena_vf_msix_mappings()
321 wr32(hw, GLINT_VECT2FUNC(v), reg); in ice_ena_vf_msix_mappings()
325 wr32(hw, VPINT_MBX_CTL(device_based_vf_id), VPINT_MBX_CTL_CAUSE_ENA_M); in ice_ena_vf_msix_mappings()
345 wr32(hw, VPLAN_TXQ_MAPENA(vf->vf_id), VPLAN_TXQ_MAPENA_TX_ENA_M); in ice_ena_vf_q_mappings()
357 wr32(hw, VPLAN_TX_QBASE(vf->vf_id), reg); in ice_ena_vf_q_mappings()
363 wr32(hw, VPLAN_RXQ_MAPENA(vf->vf_id), VPLAN_RXQ_MAPENA_RX_ENA_M); in ice_ena_vf_q_mappings()
375 wr32(hw, VPLAN_RX_QBASE(vf->vf_id), reg); in ice_ena_vf_q_mappings()
623 wr32(hw, VFGEN_RSTAT(vf->vf_id), VIRTCHNL_VFR_VFACTIVE); in ice_start_vfs()
669 wr32(hw, VFGEN_RSTAT(vf->vf_id), VIRTCHNL_VFR_INPROGRESS); in ice_sriov_clear_reset_state()
680 wr32(&pf->hw, VF_MBX_ARQLEN(vf->vf_id), 0); in ice_sriov_clear_mbx_register()
681 wr32(&pf->hw, VF_MBX_ATQLEN(vf->vf_id), 0); in ice_sriov_clear_mbx_register()
710 wr32(hw, VPGEN_VFRTRIG(vf->vf_id), reg); in ice_sriov_trigger_reset_register()
716 wr32(hw, GLGEN_VFLRSTAT(reg_idx), BIT(bit_idx)); in ice_sriov_trigger_reset_register()
719 wr32(hw, PF_PCI_CIAA, in ice_sriov_trigger_reset_register()
770 wr32(hw, VPGEN_VFRTRIG(vf->vf_id), reg); in ice_sriov_clear_reset_trigger()
799 wr32(&vf->pf->hw, VFGEN_RSTAT(vf->vf_id), VIRTCHNL_VFR_VFACTIVE); in ice_sriov_post_vsi_rebuild()
877 wr32(hw, GLINT_DYN_CTL(pf->oicr_idx), in ice_ena_vfs()