Lines Matching refs:wr32
587 wr32(E1000_I2CPARAMS, i2cctl); in igb_set_i2c_data()
610 wr32(E1000_I2CPARAMS, i2cctl); in igb_set_i2c_clk()
883 wr32(E1000_CTRL_EXT, tmp); in igb_configure_msix()
900 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | in igb_configure_msix()
908 wr32(E1000_IVAR_MISC, tmp); in igb_configure_msix()
1148 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); in igb_set_interrupt_capability()
1488 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); in igb_irq_disable()
1489 wr32(E1000_EIMC, adapter->eims_enable_mask); in igb_irq_disable()
1491 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); in igb_irq_disable()
1494 wr32(E1000_IAM, 0); in igb_irq_disable()
1495 wr32(E1000_IMC, ~0); in igb_irq_disable()
1519 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); in igb_irq_enable()
1521 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); in igb_irq_enable()
1522 wr32(E1000_EIMS, adapter->eims_enable_mask); in igb_irq_enable()
1524 wr32(E1000_MBVFIMR, 0xFF); in igb_irq_enable()
1527 wr32(E1000_IMS, ims); in igb_irq_enable()
1529 wr32(E1000_IMS, IMS_ENABLE_MASK | in igb_irq_enable()
1531 wr32(E1000_IAM, IMS_ENABLE_MASK | in igb_irq_enable()
1574 wr32(E1000_CTRL_EXT, in igb_release_hw_control()
1593 wr32(E1000_CTRL_EXT, in igb_get_hw_control()
1633 wr32(E1000_I210_TXDCTL(queue), val); in set_tx_desc_fetch_prio()
1650 wr32(E1000_I210_TQAVCC(queue), val); in set_queue_mode()
1734 wr32(E1000_I210_TQAVCTRL, tqavctrl); in igb_config_tx_modes()
1798 wr32(E1000_I210_TQAVCC(queue), tqavcc); in igb_config_tx_modes()
1800 wr32(E1000_I210_TQAVHC(queue), in igb_config_tx_modes()
1807 wr32(E1000_I210_TQAVCC(queue), tqavcc); in igb_config_tx_modes()
1810 wr32(E1000_I210_TQAVHC(queue), 0); in igb_config_tx_modes()
1819 wr32(E1000_I210_TQAVCTRL, tqavctrl); in igb_config_tx_modes()
1836 wr32(E1000_I210_TQAVCTRL, tqavctrl); in igb_config_tx_modes()
1846 wr32(E1000_I210_TQAVCTRL, tqavctrl); in igb_config_tx_modes()
1926 wr32(E1000_I210_TQAVCTRL, val); in igb_setup_tx_mode()
1935 wr32(E1000_TXPBS, val); in igb_setup_tx_mode()
1940 wr32(E1000_RXPBS, val); in igb_setup_tx_mode()
1954 wr32(E1000_I210_DTXMXPKTSZ, val); in igb_setup_tx_mode()
1968 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); in igb_setup_tx_mode()
1969 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); in igb_setup_tx_mode()
1970 wr32(E1000_I210_DTXMXPKTSZ, I210_DTXMXPKTSZ_DEFAULT); in igb_setup_tx_mode()
1978 wr32(E1000_I210_TQAVCTRL, val); in igb_setup_tx_mode()
2074 wr32(E1000_CONNSW, connsw); in igb_check_swap_media()
2082 wr32(E1000_CONNSW, connsw); in igb_check_swap_media()
2113 wr32(E1000_CTRL_EXT, ctrl_ext); in igb_check_swap_media()
2148 wr32(E1000_CTRL_EXT, reg_data); in igb_up()
2178 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); in igb_down()
2189 wr32(E1000_TCTL, tctl); in igb_down()
2254 wr32(E1000_CONNSW, connsw); in igb_enable_mas()
2271 wr32(E1000_CTRL_EXT, ctrl_ext); in igb_set_i2c_bb()
2278 wr32(E1000_I2CPARAMS, i2cctl); in igb_set_i2c_bb()
2317 wr32(E1000_PBA, pba); in igb_reset()
2355 wr32(E1000_PBA, pba); in igb_reset()
2385 wr32(E1000_VFRE, 0); in igb_reset()
2386 wr32(E1000_VFTE, 0); in igb_reset()
2391 wr32(E1000_WUC, 0); in igb_reset()
2453 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); in igb_reset()
3416 wr32(E1000_RXPBS, I210_RXPBSIZE_DEFAULT); in igb_probe()
3417 wr32(E1000_TXPBS, I210_TXPBSIZE_DEFAULT); in igb_probe()
3707 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); in igb_disable_sriov()
3856 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); in igb_remove()
4166 wr32(E1000_CTRL_EXT, reg_data); in __igb_open()
4315 wr32(E1000_TXDCTL(0), 0); in igb_setup_tctl()
4328 wr32(E1000_TCTL, tctl); in igb_setup_tctl()
4346 wr32(E1000_TDLEN(reg_idx), in igb_configure_tx_ring()
4348 wr32(E1000_TDBAL(reg_idx), in igb_configure_tx_ring()
4350 wr32(E1000_TDBAH(reg_idx), tdba >> 32); in igb_configure_tx_ring()
4353 wr32(E1000_TDH(reg_idx), 0); in igb_configure_tx_ring()
4365 wr32(E1000_TXDCTL(reg_idx), txdctl); in igb_configure_tx_ring()
4381 wr32(E1000_TXDCTL(adapter->tx_ring[i]->reg_idx), 0); in igb_configure_tx()
4483 wr32(E1000_RSSRK(j), rss_key[j]); in igb_setup_mrqc()
4517 wr32(E1000_RXCSUM, rxcsum); in igb_setup_mrqc()
4546 wr32(E1000_VT_CTL, vtctl); in igb_setup_mrqc()
4557 wr32(E1000_MRQC, mrqc); in igb_setup_mrqc()
4590 wr32(E1000_RXDCTL(0), 0); in igb_setup_rctl()
4598 wr32(E1000_QDE, ALL_QUEUES); in igb_setup_rctl()
4617 wr32(E1000_RCTL, rctl); in igb_setup_rctl()
4632 wr32(E1000_VMOLR(vfn), vmolr); in igb_set_vf_rlpml()
4656 wr32(reg, val); in igb_set_vf_vlan_strip()
4688 wr32(E1000_VMOLR(vfn), vmolr); in igb_set_vmolr()
4719 wr32(E1000_SRRCTL(reg_idx), srrctl); in igb_setup_srrctl()
4743 wr32(E1000_RXDCTL(reg_idx), 0); in igb_configure_rx_ring()
4746 wr32(E1000_RDBAL(reg_idx), in igb_configure_rx_ring()
4748 wr32(E1000_RDBAH(reg_idx), rdba >> 32); in igb_configure_rx_ring()
4749 wr32(E1000_RDLEN(reg_idx), in igb_configure_rx_ring()
4754 wr32(E1000_RDH(reg_idx), 0); in igb_configure_rx_ring()
4777 wr32(E1000_RXDCTL(reg_idx), rxdctl); in igb_configure_rx_ring()
5139 wr32(E1000_VLVF(i), vlvf); in igb_vlan_promisc_enable()
5194 wr32(E1000_VLVF(i), bits); in igb_scrub_vfta()
5294 wr32(E1000_RCTL, rctl); in igb_set_rx_mode()
5302 wr32(E1000_RLPML, rlpml); in igb_set_rx_mode()
5328 wr32(E1000_VMOLR(vfn), vmolr); in igb_set_rx_mode()
5670 wr32(E1000_EICS, eics); in igb_watchdog_task()
5672 wr32(E1000_ICS, E1000_ICS_RXDMT0); in igb_watchdog_task()
6549 wr32(E1000_EICS, in igb_tx_timeout()
6673 wr32(E1000_RQDPC(i), 0); in igb_update_stats()
6900 wr32((tsintr_tt == 1) ? E1000_TRGTTIML1 : E1000_TRGTTIML0, ts.tv_nsec); in igb_perout()
6901 wr32((tsintr_tt == 1) ? E1000_TRGTTIMH1 : E1000_TRGTTIMH0, (u32)ts.tv_sec); in igb_perout()
6904 wr32(E1000_TSAUXC, tsauxc); in igb_perout()
6980 wr32(E1000_TSICR, ack); in igb_tsync_interrupt()
7017 wr32(E1000_EIMS, adapter->eims_other); in igb_msix_other()
7073 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); in igb_update_tx_dca()
7093 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); in igb_update_rx_dca()
7124 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); in igb_setup_dca()
7160 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); in __igb_notify_dca()
7242 wr32(E1000_VMOLR(vf), vmolr); in igb_set_vf_promisc()
7300 wr32(E1000_VMOLR(i), vmolr); in igb_restore_vf_multicasts()
7352 wr32(E1000_VLVF(i), vlvf); in igb_clear_vf_vfta()
7395 wr32(E1000_VLVF(idx), BIT(pf_id)); in igb_update_pf_vlvf()
7397 wr32(E1000_VLVF(idx), 0); in igb_update_pf_vlvf()
7440 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); in igb_set_vmvir()
7442 wr32(E1000_VMVIR(vf), 0); in igb_set_vmvir()
7581 wr32(E1000_VFTE, reg | BIT(vf)); in igb_vf_reset_msg()
7583 wr32(E1000_VFRE, reg | BIT(vf)); in igb_vf_reset_msg()
8156 wr32(E1000_EIMS, q_vector->eims_value); in igb_ring_irq_enable()
9207 wr32(E1000_CTRL, ctrl); in igb_vlan_mode()
9212 wr32(E1000_RCTL, rctl); in igb_vlan_mode()
9217 wr32(E1000_CTRL, ctrl); in igb_vlan_mode()
9358 wr32(E1000_RCTL, rctl); in __igb_shutdown()
9363 wr32(E1000_CTRL, ctrl); in __igb_shutdown()
9368 wr32(E1000_WUC, E1000_WUC_PME_EN); in __igb_shutdown()
9369 wr32(E1000_WUFC, wufc); in __igb_shutdown()
9371 wr32(E1000_WUC, 0); in __igb_shutdown()
9372 wr32(E1000_WUFC, 0); in __igb_shutdown()
9470 wr32(E1000_WUS, ~0); in __igb_resume()
9651 wr32(E1000_WUS, ~0); in igb_io_slot_reset()
9730 wr32(E1000_RAL(index), rar_low); in igb_rar_set_index()
9732 wr32(E1000_RAH(index), rar_high); in igb_rar_set_index()
9825 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ in igb_set_vf_rate_limit()
9829 wr32(E1000_RTTBCNRM, 0x14); in igb_set_vf_rate_limit()
9830 wr32(E1000_RTTBCNRC, bcnrc_val); in igb_set_vf_rate_limit()
9909 wr32(reg_offset, reg_val); in igb_ndo_set_vf_spoofchk()
9965 wr32(E1000_DTXCTL, reg); in igb_vmm_control()
9971 wr32(E1000_RPLOLR, reg); in igb_vmm_control()
9999 wr32(E1000_DMCTXTH, 0); in igb_init_dmac()
10010 wr32(E1000_FCRTC, reg); in igb_init_dmac()
10030 wr32(E1000_DMACR, reg); in igb_init_dmac()
10035 wr32(E1000_DMCRTRH, 0); in igb_init_dmac()
10039 wr32(E1000_DMCTLX, reg); in igb_init_dmac()
10044 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - in igb_init_dmac()
10052 wr32(E1000_PCIEMISC, reg); in igb_init_dmac()
10057 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); in igb_init_dmac()
10058 wr32(E1000_DMACR, 0); in igb_init_dmac()