Lines Matching refs:wr32
78 wr32(IGC_GTXOFFSET, txoffset); in igc_tsn_adjust_txtime_offset()
90 wr32(IGC_GTXOFFSET, 0); in igc_tsn_disable_offload()
91 wr32(IGC_TXPBS, I225_TXPBSIZE_DEFAULT); in igc_tsn_disable_offload()
92 wr32(IGC_DTXMXPKTSZ, IGC_DTXMXPKTSZ_DEFAULT); in igc_tsn_disable_offload()
98 wr32(IGC_TQAVCTRL, tqavctrl); in igc_tsn_disable_offload()
101 wr32(IGC_TXQCTL(i), 0); in igc_tsn_disable_offload()
102 wr32(IGC_STQT(i), 0); in igc_tsn_disable_offload()
103 wr32(IGC_ENDQT(i), NSEC_PER_SEC); in igc_tsn_disable_offload()
106 wr32(IGC_QBVCYCLET_S, 0); in igc_tsn_disable_offload()
107 wr32(IGC_QBVCYCLET, NSEC_PER_SEC); in igc_tsn_disable_offload()
122 wr32(IGC_TSAUXC, 0); in igc_tsn_enable_offload()
123 wr32(IGC_DTXMXPKTSZ, IGC_DTXMXPKTSZ_TSN); in igc_tsn_enable_offload()
124 wr32(IGC_TXPBS, IGC_TXPBSIZE_TSN); in igc_tsn_enable_offload()
132 wr32(IGC_STQT(i), ring->start_time); in igc_tsn_enable_offload()
133 wr32(IGC_ENDQT(i), ring->end_time); in igc_tsn_enable_offload()
207 wr32(IGC_TQAVCC(i), tqavcc); in igc_tsn_enable_offload()
209 wr32(IGC_TQAVHC(i), in igc_tsn_enable_offload()
219 wr32(IGC_TQAVCC(i), tqavcc); in igc_tsn_enable_offload()
222 wr32(IGC_TQAVHC(i), 0); in igc_tsn_enable_offload()
225 wr32(IGC_TXQCTL(i), txqctl); in igc_tsn_enable_offload()
253 wr32(IGC_TQAVCTRL, tqavctrl); in igc_tsn_enable_offload()
255 wr32(IGC_QBVCYCLET_S, cycle); in igc_tsn_enable_offload()
256 wr32(IGC_QBVCYCLET, cycle); in igc_tsn_enable_offload()
259 wr32(IGC_BASET_H, baset_h); in igc_tsn_enable_offload()
267 wr32(IGC_BASET_L, 0); in igc_tsn_enable_offload()
268 wr32(IGC_BASET_L, baset_l); in igc_tsn_enable_offload()