Lines Matching refs:hw
18 static u32 ixgb_hash_mc_addr(struct ixgb_hw *hw, u8 * mc_addr);
20 static void ixgb_mta_set(struct ixgb_hw *hw, u32 hash_value);
22 static void ixgb_get_bus_info(struct ixgb_hw *hw);
24 static bool ixgb_link_reset(struct ixgb_hw *hw);
26 static void ixgb_optics_reset(struct ixgb_hw *hw);
28 static void ixgb_optics_reset_bcm(struct ixgb_hw *hw);
30 static ixgb_phy_type ixgb_identify_phy(struct ixgb_hw *hw);
32 static void ixgb_clear_hw_cntrs(struct ixgb_hw *hw);
34 static void ixgb_clear_vfta(struct ixgb_hw *hw);
36 static void ixgb_init_rx_addrs(struct ixgb_hw *hw);
38 static u16 ixgb_read_phy_reg(struct ixgb_hw *hw,
43 static bool ixgb_setup_fc(struct ixgb_hw *hw);
47 static u32 ixgb_mac_reset(struct ixgb_hw *hw) in ixgb_mac_reset() argument
62 IXGB_WRITE_REG_IO(hw, CTRL0, ctrl_reg); in ixgb_mac_reset()
64 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg); in ixgb_mac_reset()
69 ctrl_reg = IXGB_READ_REG(hw, CTRL0); in ixgb_mac_reset()
75 if (hw->subsystem_vendor_id == PCI_VENDOR_ID_SUN) { in ixgb_mac_reset()
82 IXGB_WRITE_REG(hw, CTRL1, ctrl_reg); in ixgb_mac_reset()
83 ixgb_optics_reset_bcm(hw); in ixgb_mac_reset()
86 if (hw->phy_type == ixgb_phy_type_txn17401) in ixgb_mac_reset()
87 ixgb_optics_reset(hw); in ixgb_mac_reset()
98 ixgb_adapter_stop(struct ixgb_hw *hw) in ixgb_adapter_stop() argument
107 if (hw->adapter_stopped) { in ixgb_adapter_stop()
115 hw->adapter_stopped = true; in ixgb_adapter_stop()
119 IXGB_WRITE_REG(hw, IMC, 0xFFFFFFFF); in ixgb_adapter_stop()
125 IXGB_WRITE_REG(hw, RCTL, IXGB_READ_REG(hw, RCTL) & ~IXGB_RCTL_RXEN); in ixgb_adapter_stop()
126 IXGB_WRITE_REG(hw, TCTL, IXGB_READ_REG(hw, TCTL) & ~IXGB_TCTL_TXEN); in ixgb_adapter_stop()
127 IXGB_WRITE_FLUSH(hw); in ixgb_adapter_stop()
137 ctrl_reg = ixgb_mac_reset(hw); in ixgb_adapter_stop()
141 IXGB_WRITE_REG(hw, IMC, 0xffffffff); in ixgb_adapter_stop()
144 IXGB_READ_REG(hw, ICR); in ixgb_adapter_stop()
160 ixgb_identify_xpak_vendor(struct ixgb_hw *hw) in ixgb_identify_xpak_vendor() argument
172 vendor_name[i] = ixgb_read_phy_reg(hw, in ixgb_identify_xpak_vendor()
200 ixgb_identify_phy(struct ixgb_hw *hw) in ixgb_identify_phy() argument
208 switch (hw->device_id) { in ixgb_identify_phy()
218 xpak_vendor = ixgb_identify_xpak_vendor(hw); in ixgb_identify_phy()
233 xpak_vendor = ixgb_identify_xpak_vendor(hw); in ixgb_identify_phy()
249 if (hw->subsystem_vendor_id == PCI_VENDOR_ID_SUN) in ixgb_identify_phy()
273 ixgb_init_hw(struct ixgb_hw *hw) in ixgb_init_hw() argument
287 ixgb_mac_reset(hw); in ixgb_init_hw()
292 IXGB_WRITE_REG_IO(hw, CTRL1, IXGB_CTRL1_EE_RST); in ixgb_init_hw()
294 IXGB_WRITE_REG(hw, CTRL1, IXGB_CTRL1_EE_RST); in ixgb_init_hw()
300 if (!ixgb_get_eeprom_data(hw)) in ixgb_init_hw()
304 hw->device_id = ixgb_get_ee_device_id(hw); in ixgb_init_hw()
305 hw->phy_type = ixgb_identify_phy(hw); in ixgb_init_hw()
310 ixgb_init_rx_addrs(hw); in ixgb_init_hw()
316 if (!mac_addr_valid(hw->curr_mac_addr)) { in ixgb_init_hw()
322 hw->adapter_stopped = false; in ixgb_init_hw()
325 ixgb_get_bus_info(hw); in ixgb_init_hw()
330 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0); in ixgb_init_hw()
333 ixgb_clear_vfta(hw); in ixgb_init_hw()
336 ixgb_clear_hw_cntrs(hw); in ixgb_init_hw()
339 status = ixgb_setup_fc(hw); in ixgb_init_hw()
342 ixgb_check_for_link(hw); in ixgb_init_hw()
357 ixgb_init_rx_addrs(struct ixgb_hw *hw) in ixgb_init_rx_addrs() argument
368 if (!mac_addr_valid(hw->curr_mac_addr)) { in ixgb_init_rx_addrs()
371 ixgb_get_ee_mac_addr(hw, hw->curr_mac_addr); in ixgb_init_rx_addrs()
374 hw->curr_mac_addr); in ixgb_init_rx_addrs()
379 pr_debug("New MAC Addr = %pM\n", hw->curr_mac_addr); in ixgb_init_rx_addrs()
381 ixgb_rar_set(hw, hw->curr_mac_addr, 0); in ixgb_init_rx_addrs()
388 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); in ixgb_init_rx_addrs()
389 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); in ixgb_init_rx_addrs()
407 ixgb_mc_addr_list_update(struct ixgb_hw *hw, in ixgb_mc_addr_list_update() argument
420 hw->num_mc_addrs = mc_addr_count; in ixgb_mc_addr_list_update()
425 IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); in ixgb_mc_addr_list_update()
426 IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); in ixgb_mc_addr_list_update()
432 IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0); in ixgb_mc_addr_list_update()
444 ixgb_rar_set(hw, mca, rar_used_count); in ixgb_mc_addr_list_update()
448 hash_value = ixgb_hash_mc_addr(hw, mca); in ixgb_mc_addr_list_update()
452 ixgb_mta_set(hw, hash_value); in ixgb_mc_addr_list_update()
471 ixgb_hash_mc_addr(struct ixgb_hw *hw, in ixgb_hash_mc_addr() argument
481 switch (hw->mc_filter_type) { in ixgb_hash_mc_addr()
519 ixgb_mta_set(struct ixgb_hw *hw, in ixgb_mta_set() argument
536 mta_reg = IXGB_READ_REG_ARRAY(hw, MTA, hash_reg); in ixgb_mta_set()
540 IXGB_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta_reg); in ixgb_mta_set()
551 ixgb_rar_set(struct ixgb_hw *hw, in ixgb_rar_set() argument
571 IXGB_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); in ixgb_rar_set()
572 IXGB_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); in ixgb_rar_set()
583 ixgb_write_vfta(struct ixgb_hw *hw, in ixgb_write_vfta() argument
587 IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, value); in ixgb_write_vfta()
596 ixgb_clear_vfta(struct ixgb_hw *hw) in ixgb_clear_vfta() argument
601 IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, 0); in ixgb_clear_vfta()
611 ixgb_setup_fc(struct ixgb_hw *hw) in ixgb_setup_fc() argument
620 ctrl_reg = IXGB_READ_REG(hw, CTRL0); in ixgb_setup_fc()
634 switch (hw->fc.type) { in ixgb_setup_fc()
650 pap_reg = hw->fc.pause_time; in ixgb_setup_fc()
657 pap_reg = hw->fc.pause_time; in ixgb_setup_fc()
667 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg); in ixgb_setup_fc()
670 IXGB_WRITE_REG(hw, PAP, pap_reg); in ixgb_setup_fc()
678 if (!(hw->fc.type & ixgb_fc_tx_pause)) { in ixgb_setup_fc()
679 IXGB_WRITE_REG(hw, FCRTL, 0); in ixgb_setup_fc()
680 IXGB_WRITE_REG(hw, FCRTH, 0); in ixgb_setup_fc()
685 if (hw->fc.send_xon) { in ixgb_setup_fc()
686 IXGB_WRITE_REG(hw, FCRTL, in ixgb_setup_fc()
687 (hw->fc.low_water | IXGB_FCRTL_XONE)); in ixgb_setup_fc()
689 IXGB_WRITE_REG(hw, FCRTL, hw->fc.low_water); in ixgb_setup_fc()
691 IXGB_WRITE_REG(hw, FCRTH, hw->fc.high_water); in ixgb_setup_fc()
712 ixgb_read_phy_reg(struct ixgb_hw *hw, in ixgb_read_phy_reg() argument
731 IXGB_WRITE_REG(hw, MSCA, command); in ixgb_read_phy_reg()
744 command = IXGB_READ_REG(hw, MSCA); in ixgb_read_phy_reg()
758 IXGB_WRITE_REG(hw, MSCA, command); in ixgb_read_phy_reg()
771 command = IXGB_READ_REG(hw, MSCA); in ixgb_read_phy_reg()
782 data = IXGB_READ_REG(hw, MSRWD); in ixgb_read_phy_reg()
805 ixgb_write_phy_reg(struct ixgb_hw *hw, in ixgb_write_phy_reg() argument
819 IXGB_WRITE_REG(hw, MSRWD, (u32)data); in ixgb_write_phy_reg()
827 IXGB_WRITE_REG(hw, MSCA, command); in ixgb_write_phy_reg()
840 command = IXGB_READ_REG(hw, MSCA); in ixgb_write_phy_reg()
854 IXGB_WRITE_REG(hw, MSCA, command); in ixgb_write_phy_reg()
867 command = IXGB_READ_REG(hw, MSCA); in ixgb_write_phy_reg()
886 ixgb_check_for_link(struct ixgb_hw *hw) in ixgb_check_for_link() argument
893 xpcss_reg = IXGB_READ_REG(hw, XPCSS); in ixgb_check_for_link()
894 status_reg = IXGB_READ_REG(hw, STATUS); in ixgb_check_for_link()
898 hw->link_up = true; in ixgb_check_for_link()
902 hw->link_up = ixgb_link_reset(hw); in ixgb_check_for_link()
908 hw->link_up = ixgb_link_reset(hw); in ixgb_check_for_link()
922 bool ixgb_check_for_bad_link(struct ixgb_hw *hw) in ixgb_check_for_bad_link() argument
927 if (hw->phy_type == ixgb_phy_type_txn17401) { in ixgb_check_for_bad_link()
928 newLFC = IXGB_READ_REG(hw, LFC); in ixgb_check_for_bad_link()
929 newRFC = IXGB_READ_REG(hw, RFC); in ixgb_check_for_bad_link()
930 if ((hw->lastLFC + 250 < newLFC) in ixgb_check_for_bad_link()
931 || (hw->lastRFC + 250 < newRFC)) { in ixgb_check_for_bad_link()
935 hw->lastLFC = newLFC; in ixgb_check_for_bad_link()
936 hw->lastRFC = newRFC; in ixgb_check_for_bad_link()
948 ixgb_clear_hw_cntrs(struct ixgb_hw *hw) in ixgb_clear_hw_cntrs() argument
953 if (hw->adapter_stopped) { in ixgb_clear_hw_cntrs()
958 IXGB_READ_REG(hw, TPRL); in ixgb_clear_hw_cntrs()
959 IXGB_READ_REG(hw, TPRH); in ixgb_clear_hw_cntrs()
960 IXGB_READ_REG(hw, GPRCL); in ixgb_clear_hw_cntrs()
961 IXGB_READ_REG(hw, GPRCH); in ixgb_clear_hw_cntrs()
962 IXGB_READ_REG(hw, BPRCL); in ixgb_clear_hw_cntrs()
963 IXGB_READ_REG(hw, BPRCH); in ixgb_clear_hw_cntrs()
964 IXGB_READ_REG(hw, MPRCL); in ixgb_clear_hw_cntrs()
965 IXGB_READ_REG(hw, MPRCH); in ixgb_clear_hw_cntrs()
966 IXGB_READ_REG(hw, UPRCL); in ixgb_clear_hw_cntrs()
967 IXGB_READ_REG(hw, UPRCH); in ixgb_clear_hw_cntrs()
968 IXGB_READ_REG(hw, VPRCL); in ixgb_clear_hw_cntrs()
969 IXGB_READ_REG(hw, VPRCH); in ixgb_clear_hw_cntrs()
970 IXGB_READ_REG(hw, JPRCL); in ixgb_clear_hw_cntrs()
971 IXGB_READ_REG(hw, JPRCH); in ixgb_clear_hw_cntrs()
972 IXGB_READ_REG(hw, GORCL); in ixgb_clear_hw_cntrs()
973 IXGB_READ_REG(hw, GORCH); in ixgb_clear_hw_cntrs()
974 IXGB_READ_REG(hw, TORL); in ixgb_clear_hw_cntrs()
975 IXGB_READ_REG(hw, TORH); in ixgb_clear_hw_cntrs()
976 IXGB_READ_REG(hw, RNBC); in ixgb_clear_hw_cntrs()
977 IXGB_READ_REG(hw, RUC); in ixgb_clear_hw_cntrs()
978 IXGB_READ_REG(hw, ROC); in ixgb_clear_hw_cntrs()
979 IXGB_READ_REG(hw, RLEC); in ixgb_clear_hw_cntrs()
980 IXGB_READ_REG(hw, CRCERRS); in ixgb_clear_hw_cntrs()
981 IXGB_READ_REG(hw, ICBC); in ixgb_clear_hw_cntrs()
982 IXGB_READ_REG(hw, ECBC); in ixgb_clear_hw_cntrs()
983 IXGB_READ_REG(hw, MPC); in ixgb_clear_hw_cntrs()
984 IXGB_READ_REG(hw, TPTL); in ixgb_clear_hw_cntrs()
985 IXGB_READ_REG(hw, TPTH); in ixgb_clear_hw_cntrs()
986 IXGB_READ_REG(hw, GPTCL); in ixgb_clear_hw_cntrs()
987 IXGB_READ_REG(hw, GPTCH); in ixgb_clear_hw_cntrs()
988 IXGB_READ_REG(hw, BPTCL); in ixgb_clear_hw_cntrs()
989 IXGB_READ_REG(hw, BPTCH); in ixgb_clear_hw_cntrs()
990 IXGB_READ_REG(hw, MPTCL); in ixgb_clear_hw_cntrs()
991 IXGB_READ_REG(hw, MPTCH); in ixgb_clear_hw_cntrs()
992 IXGB_READ_REG(hw, UPTCL); in ixgb_clear_hw_cntrs()
993 IXGB_READ_REG(hw, UPTCH); in ixgb_clear_hw_cntrs()
994 IXGB_READ_REG(hw, VPTCL); in ixgb_clear_hw_cntrs()
995 IXGB_READ_REG(hw, VPTCH); in ixgb_clear_hw_cntrs()
996 IXGB_READ_REG(hw, JPTCL); in ixgb_clear_hw_cntrs()
997 IXGB_READ_REG(hw, JPTCH); in ixgb_clear_hw_cntrs()
998 IXGB_READ_REG(hw, GOTCL); in ixgb_clear_hw_cntrs()
999 IXGB_READ_REG(hw, GOTCH); in ixgb_clear_hw_cntrs()
1000 IXGB_READ_REG(hw, TOTL); in ixgb_clear_hw_cntrs()
1001 IXGB_READ_REG(hw, TOTH); in ixgb_clear_hw_cntrs()
1002 IXGB_READ_REG(hw, DC); in ixgb_clear_hw_cntrs()
1003 IXGB_READ_REG(hw, PLT64C); in ixgb_clear_hw_cntrs()
1004 IXGB_READ_REG(hw, TSCTC); in ixgb_clear_hw_cntrs()
1005 IXGB_READ_REG(hw, TSCTFC); in ixgb_clear_hw_cntrs()
1006 IXGB_READ_REG(hw, IBIC); in ixgb_clear_hw_cntrs()
1007 IXGB_READ_REG(hw, RFC); in ixgb_clear_hw_cntrs()
1008 IXGB_READ_REG(hw, LFC); in ixgb_clear_hw_cntrs()
1009 IXGB_READ_REG(hw, PFRC); in ixgb_clear_hw_cntrs()
1010 IXGB_READ_REG(hw, PFTC); in ixgb_clear_hw_cntrs()
1011 IXGB_READ_REG(hw, MCFRC); in ixgb_clear_hw_cntrs()
1012 IXGB_READ_REG(hw, MCFTC); in ixgb_clear_hw_cntrs()
1013 IXGB_READ_REG(hw, XONRXC); in ixgb_clear_hw_cntrs()
1014 IXGB_READ_REG(hw, XONTXC); in ixgb_clear_hw_cntrs()
1015 IXGB_READ_REG(hw, XOFFRXC); in ixgb_clear_hw_cntrs()
1016 IXGB_READ_REG(hw, XOFFTXC); in ixgb_clear_hw_cntrs()
1017 IXGB_READ_REG(hw, RJC); in ixgb_clear_hw_cntrs()
1026 ixgb_led_on(struct ixgb_hw *hw) in ixgb_led_on() argument
1028 u32 ctrl0_reg = IXGB_READ_REG(hw, CTRL0); in ixgb_led_on()
1032 IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg); in ixgb_led_on()
1041 ixgb_led_off(struct ixgb_hw *hw) in ixgb_led_off() argument
1043 u32 ctrl0_reg = IXGB_READ_REG(hw, CTRL0); in ixgb_led_off()
1047 IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg); in ixgb_led_off()
1056 ixgb_get_bus_info(struct ixgb_hw *hw) in ixgb_get_bus_info() argument
1060 status_reg = IXGB_READ_REG(hw, STATUS); in ixgb_get_bus_info()
1062 hw->bus.type = (status_reg & IXGB_STATUS_PCIX_MODE) ? in ixgb_get_bus_info()
1065 if (hw->bus.type == ixgb_bus_type_pci) { in ixgb_get_bus_info()
1066 hw->bus.speed = (status_reg & IXGB_STATUS_PCI_SPD) ? in ixgb_get_bus_info()
1071 hw->bus.speed = ixgb_bus_speed_66; in ixgb_get_bus_info()
1074 hw->bus.speed = ixgb_bus_speed_100; in ixgb_get_bus_info()
1077 hw->bus.speed = ixgb_bus_speed_133; in ixgb_get_bus_info()
1080 hw->bus.speed = ixgb_bus_speed_reserved; in ixgb_get_bus_info()
1085 hw->bus.width = (status_reg & IXGB_STATUS_BUS64) ? in ixgb_get_bus_info()
1126 ixgb_link_reset(struct ixgb_hw *hw) in ixgb_link_reset() argument
1134 IXGB_WRITE_REG(hw, CTRL0, in ixgb_link_reset()
1135 IXGB_READ_REG(hw, CTRL0) | IXGB_CTRL0_LRST); in ixgb_link_reset()
1141 ((IXGB_READ_REG(hw, STATUS) & IXGB_STATUS_LU) in ixgb_link_reset()
1142 && (IXGB_READ_REG(hw, XPCSS) & in ixgb_link_reset()
1157 ixgb_optics_reset(struct ixgb_hw *hw) in ixgb_optics_reset() argument
1159 if (hw->phy_type == ixgb_phy_type_txn17401) { in ixgb_optics_reset()
1160 ixgb_write_phy_reg(hw, in ixgb_optics_reset()
1166 ixgb_read_phy_reg(hw, MDIO_CTRL1, IXGB_PHY_ADDRESS, MDIO_MMD_PMAPMD); in ixgb_optics_reset()
1185 ixgb_optics_reset_bcm(struct ixgb_hw *hw) in ixgb_optics_reset_bcm() argument
1187 u32 ctrl = IXGB_READ_REG(hw, CTRL0); in ixgb_optics_reset_bcm()
1190 IXGB_WRITE_REG(hw, CTRL0, ctrl); in ixgb_optics_reset_bcm()
1191 IXGB_WRITE_FLUSH(hw); in ixgb_optics_reset_bcm()
1198 ixgb_write_phy_reg(hw, in ixgb_optics_reset_bcm()
1204 ixgb_read_phy_reg(hw, in ixgb_optics_reset_bcm()
1208 ixgb_read_phy_reg(hw, in ixgb_optics_reset_bcm()
1213 ixgb_write_phy_reg(hw, in ixgb_optics_reset_bcm()
1218 ixgb_read_phy_reg(hw, in ixgb_optics_reset_bcm()
1222 ixgb_read_phy_reg(hw, in ixgb_optics_reset_bcm()