Lines Matching refs:reg_idx
200 u32 head = IXGBE_READ_REG(hw, IXGBE_VFTDH(ring->reg_idx)); in ixgbevf_get_tx_pending()
201 u32 tail = IXGBE_READ_REG(hw, IXGBE_VFTDT(ring->reg_idx)); in ixgbevf_get_tx_pending()
385 IXGBE_READ_REG(hw, IXGBE_VFTDH(tx_ring->reg_idx)), in ixgbevf_clean_tx_irq()
386 IXGBE_READ_REG(hw, IXGBE_VFTDT(tx_ring->reg_idx)), in ixgbevf_clean_tx_irq()
1365 ixgbevf_set_ivar(adapter, 0, ring->reg_idx, v_idx); in ixgbevf_configure_msix()
1368 ixgbevf_set_ivar(adapter, 1, ring->reg_idx, v_idx); in ixgbevf_configure_msix()
1691 u8 reg_idx = ring->reg_idx; in ixgbevf_configure_tx_ring() local
1694 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); in ixgbevf_configure_tx_ring()
1697 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(reg_idx), tdba & DMA_BIT_MASK(32)); in ixgbevf_configure_tx_ring()
1698 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(reg_idx), tdba >> 32); in ixgbevf_configure_tx_ring()
1699 IXGBE_WRITE_REG(hw, IXGBE_VFTDLEN(reg_idx), in ixgbevf_configure_tx_ring()
1703 IXGBE_WRITE_REG(hw, IXGBE_VFTDWBAH(reg_idx), 0); in ixgbevf_configure_tx_ring()
1704 IXGBE_WRITE_REG(hw, IXGBE_VFTDWBAL(reg_idx), 0); in ixgbevf_configure_tx_ring()
1707 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_TXCTRL(reg_idx), in ixgbevf_configure_tx_ring()
1712 IXGBE_WRITE_REG(hw, IXGBE_VFTDH(reg_idx), 0); in ixgbevf_configure_tx_ring()
1713 IXGBE_WRITE_REG(hw, IXGBE_VFTDT(reg_idx), 0); in ixgbevf_configure_tx_ring()
1714 ring->tail = adapter->io_addr + IXGBE_VFTDT(reg_idx); in ixgbevf_configure_tx_ring()
1737 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(reg_idx), txdctl); in ixgbevf_configure_tx_ring()
1742 txdctl = IXGBE_READ_REG(hw, IXGBE_VFTXDCTL(reg_idx)); in ixgbevf_configure_tx_ring()
1745 hw_dbg(hw, "Could not enable Tx Queue %d\n", reg_idx); in ixgbevf_configure_tx_ring()
1807 u8 reg_idx = ring->reg_idx; in ixgbevf_disable_rx_queue() local
1811 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(reg_idx)); in ixgbevf_disable_rx_queue()
1815 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(reg_idx), rxdctl); in ixgbevf_disable_rx_queue()
1820 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(reg_idx)); in ixgbevf_disable_rx_queue()
1825 reg_idx); in ixgbevf_disable_rx_queue()
1834 u8 reg_idx = ring->reg_idx; in ixgbevf_rx_desc_queue_enable() local
1840 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(reg_idx)); in ixgbevf_rx_desc_queue_enable()
1845 reg_idx); in ixgbevf_rx_desc_queue_enable()
1912 u8 reg_idx = ring->reg_idx; in ixgbevf_configure_rx_ring() local
1915 rxdctl = IXGBE_READ_REG(hw, IXGBE_VFRXDCTL(reg_idx)); in ixgbevf_configure_rx_ring()
1918 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAL(reg_idx), rdba & DMA_BIT_MASK(32)); in ixgbevf_configure_rx_ring()
1919 IXGBE_WRITE_REG(hw, IXGBE_VFRDBAH(reg_idx), rdba >> 32); in ixgbevf_configure_rx_ring()
1920 IXGBE_WRITE_REG(hw, IXGBE_VFRDLEN(reg_idx), in ixgbevf_configure_rx_ring()
1925 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_RXCTRL(reg_idx), in ixgbevf_configure_rx_ring()
1928 IXGBE_WRITE_REG(hw, IXGBE_VFDCA_RXCTRL(reg_idx), in ixgbevf_configure_rx_ring()
1934 IXGBE_WRITE_REG(hw, IXGBE_VFRDH(reg_idx), 0); in ixgbevf_configure_rx_ring()
1935 IXGBE_WRITE_REG(hw, IXGBE_VFRDT(reg_idx), 0); in ixgbevf_configure_rx_ring()
1936 ring->tail = adapter->io_addr + IXGBE_VFRDT(reg_idx); in ixgbevf_configure_rx_ring()
1951 ixgbevf_configure_srrctl(adapter, ring, reg_idx); in ixgbevf_configure_rx_ring()
1968 IXGBE_WRITE_REG(hw, IXGBE_VFRXDCTL(reg_idx), rxdctl); in ixgbevf_configure_rx_ring()
2203 adapter->tx_ring[0]->reg_idx = def_q; in ixgbevf_configure_dcb()
2520 u8 reg_idx = adapter->tx_ring[i]->reg_idx; in ixgbevf_down() local
2522 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(reg_idx), in ixgbevf_down()
2527 u8 reg_idx = adapter->xdp_ring[i]->reg_idx; in ixgbevf_down() local
2529 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(reg_idx), in ixgbevf_down()
2730 int reg_idx = txr_idx + xdp_idx; in ixgbevf_alloc_q_vector() local
2767 ring->reg_idx = reg_idx; in ixgbevf_alloc_q_vector()
2775 reg_idx++; in ixgbevf_alloc_q_vector()
2795 ring->reg_idx = reg_idx; in ixgbevf_alloc_q_vector()
2804 reg_idx++; in ixgbevf_alloc_q_vector()
2824 ring->reg_idx = rxr_idx; in ixgbevf_alloc_q_vector()