Lines Matching refs:msg_rsp
128 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp) \
129 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp) \
132 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \
136 msg_rsp) \
137 M(SET_VF_PERM, 0x00b, set_vf_perm, set_vf_perm, msg_rsp) \
139 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \
140 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \
146 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \
147 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \
148 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \
149 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \
151 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \
152 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \
153 M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \
154 M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \
162 msg_rsp) \
168 M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, msg_rsp) \
173 msg_rsp) \
181 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \
183 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\
188 msg_rsp) \
189 M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \
193 cpt_inline_ipsec_cfg_msg, msg_rsp) \
196 msg_rsp) \
197 M(CPT_CTX_CACHE_SYNC, 0xA07, cpt_ctx_cache_sync, msg_req, msg_rsp) \
198 M(CPT_LF_RESET, 0xA08, cpt_lf_reset, cpt_lf_rst_req, msg_rsp) \
202 M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg, msg_rsp) \
208 npc_mcam_free_entry_req, msg_rsp) \
210 npc_mcam_write_entry_req, msg_rsp) \
212 npc_mcam_ena_dis_entry_req, msg_rsp) \
214 npc_mcam_ena_dis_entry_req, msg_rsp) \
221 npc_mcam_oper_counter_req, msg_rsp) \
223 npc_mcam_unmap_counter_req, msg_rsp) \
225 npc_mcam_oper_counter_req, msg_rsp) \
237 npc_delete_flow_req, msg_rsp) \
242 npc_set_pkind, msg_rsp) \
257 M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \
260 hwctx_disable_req, msg_rsp) \
263 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \
266 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \
272 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \
273 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \
274 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \
275 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \
276 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \
280 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \
284 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, msg_rsp) \
285 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, msg_rsp) \
288 M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \
291 nix_inline_ipsec_cfg, msg_rsp) \
293 nix_inline_ipsec_lf_cfg, msg_rsp) \
300 msg_rsp) \
308 M(MCS_FREE_RESOURCES, 0xa001, mcs_free_resources, mcs_free_rsrc_req, msg_rsp) \
310 msg_rsp) \
312 msg_rsp) \
314 msg_rsp) \
316 msg_rsp) \
318 msg_rsp) \
320 msg_rsp) \
322 msg_rsp) \
324 msg_rsp) \
326 msg_rsp) \
336 M(MCS_CLEAR_STATS, 0xa011, mcs_clear_stats, mcs_clear_stats, msg_rsp) \
337 M(MCS_INTR_CFG, 0xa012, mcs_intr_cfg, mcs_intr_cfg, msg_rsp) \
338 M(MCS_SET_LMAC_MODE, 0xa013, mcs_set_lmac_mode, mcs_set_lmac_mode, msg_rsp) \
340 msg_rsp) \
345 mcs_free_ctrl_pkt_rule_req, msg_rsp) \
347 mcs_ctrl_pkt_rule_write_req, msg_rsp) \
348 M(MCS_PORT_RESET, 0xa018, mcs_port_reset, mcs_port_reset_req, msg_rsp) \
349 M(MCS_PORT_CFG_SET, 0xa019, mcs_port_cfg_set, mcs_port_cfg_set_req, msg_rsp)\
358 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp)
361 M(CPT_INST_LMTST, 0xD00, cpt_inst_lmtst, cpt_inst_lmtst_req, msg_rsp)
364 M(MCS_INTR_NOTIFY, 0xE00, mcs_intr_notify, mcs_intr_info, msg_rsp)
389 struct msg_rsp { struct