Lines Matching refs:mcs
27 void mcs_get_tx_secy_stats(struct mcs *mcs, struct mcs_secy_stats *stats, int id) in mcs_get_tx_secy_stats() argument
32 stats->ctl_pkt_bcast_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
35 stats->ctl_pkt_mcast_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
38 stats->ctl_octet_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
41 stats->ctl_pkt_ucast_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
44 stats->unctl_pkt_bcast_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
47 stats->unctl_pkt_mcast_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
50 stats->unctl_octet_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
53 stats->unctl_pkt_ucast_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
56 stats->octet_encrypted_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
59 stats->octet_protected_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
62 stats->pkt_noactivesa_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
65 stats->pkt_toolong_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
68 stats->pkt_untagged_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
71 void mcs_get_rx_secy_stats(struct mcs *mcs, struct mcs_secy_stats *stats, int id) in mcs_get_rx_secy_stats() argument
76 stats->ctl_pkt_bcast_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
79 stats->ctl_pkt_mcast_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
82 stats->ctl_octet_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
85 stats->ctl_pkt_ucast_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
88 stats->unctl_pkt_bcast_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
91 stats->unctl_pkt_mcast_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
94 stats->unctl_octet_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
97 stats->unctl_pkt_ucast_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
100 stats->octet_decrypted_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
103 stats->octet_validated_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
106 stats->pkt_port_disabled_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
109 stats->pkt_badtag_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
112 stats->pkt_nosa_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
115 stats->pkt_nosaerror_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
118 stats->pkt_tagged_ctl_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
121 stats->pkt_untaged_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
124 stats->pkt_ctl_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
126 if (mcs->hw->mcs_blks > 1) { in mcs_get_rx_secy_stats()
128 stats->pkt_notag_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
132 void mcs_get_flowid_stats(struct mcs *mcs, struct mcs_flowid_stats *stats, in mcs_get_flowid_stats() argument
142 stats->tcam_hit_cnt = mcs_reg_read(mcs, reg); in mcs_get_flowid_stats()
145 void mcs_get_port_stats(struct mcs *mcs, struct mcs_port_stats *stats, in mcs_get_port_stats() argument
152 stats->tcam_miss_cnt = mcs_reg_read(mcs, reg); in mcs_get_port_stats()
155 stats->parser_err_cnt = mcs_reg_read(mcs, reg); in mcs_get_port_stats()
156 if (mcs->hw->mcs_blks > 1) { in mcs_get_port_stats()
158 stats->preempt_err_cnt = mcs_reg_read(mcs, reg); in mcs_get_port_stats()
162 stats->tcam_miss_cnt = mcs_reg_read(mcs, reg); in mcs_get_port_stats()
165 stats->parser_err_cnt = mcs_reg_read(mcs, reg); in mcs_get_port_stats()
168 stats->sectag_insert_err_cnt = mcs_reg_read(mcs, reg); in mcs_get_port_stats()
172 void mcs_get_sa_stats(struct mcs *mcs, struct mcs_sa_stats *stats, int id, int dir) in mcs_get_sa_stats() argument
178 stats->pkt_invalid_cnt = mcs_reg_read(mcs, reg); in mcs_get_sa_stats()
181 stats->pkt_nosaerror_cnt = mcs_reg_read(mcs, reg); in mcs_get_sa_stats()
184 stats->pkt_notvalid_cnt = mcs_reg_read(mcs, reg); in mcs_get_sa_stats()
187 stats->pkt_ok_cnt = mcs_reg_read(mcs, reg); in mcs_get_sa_stats()
190 stats->pkt_nosa_cnt = mcs_reg_read(mcs, reg); in mcs_get_sa_stats()
193 stats->pkt_encrypt_cnt = mcs_reg_read(mcs, reg); in mcs_get_sa_stats()
196 stats->pkt_protected_cnt = mcs_reg_read(mcs, reg); in mcs_get_sa_stats()
200 void mcs_get_sc_stats(struct mcs *mcs, struct mcs_sc_stats *stats, in mcs_get_sc_stats() argument
207 stats->hit_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
210 stats->pkt_invalid_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
213 stats->pkt_late_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
216 stats->pkt_notvalid_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
219 stats->pkt_unchecked_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
221 if (mcs->hw->mcs_blks > 1) { in mcs_get_sc_stats()
223 stats->pkt_delay_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
226 stats->pkt_ok_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
228 if (mcs->hw->mcs_blks == 1) { in mcs_get_sc_stats()
230 stats->octet_decrypt_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
233 stats->octet_validate_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
237 stats->pkt_encrypt_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
240 stats->pkt_protected_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
242 if (mcs->hw->mcs_blks == 1) { in mcs_get_sc_stats()
244 stats->octet_encrypt_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
247 stats->octet_protected_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
252 void mcs_clear_stats(struct mcs *mcs, u8 type, u8 id, int dir) in mcs_clear_stats() argument
266 mcs_reg_write(mcs, reg, BIT_ULL(0)); in mcs_clear_stats()
270 mcs_get_flowid_stats(mcs, &flowid_st, id, dir); in mcs_clear_stats()
274 mcs_get_rx_secy_stats(mcs, &secy_st, id); in mcs_clear_stats()
276 mcs_get_tx_secy_stats(mcs, &secy_st, id); in mcs_clear_stats()
279 mcs_get_sc_stats(mcs, &sc_st, id, dir); in mcs_clear_stats()
282 mcs_get_sa_stats(mcs, &sa_st, id, dir); in mcs_clear_stats()
285 mcs_get_port_stats(mcs, &port_st, id, dir); in mcs_clear_stats()
289 mcs_reg_write(mcs, reg, 0x0); in mcs_clear_stats()
292 int mcs_clear_all_stats(struct mcs *mcs, u16 pcifunc, int dir) in mcs_clear_all_stats() argument
298 map = &mcs->rx; in mcs_clear_all_stats()
300 map = &mcs->tx; in mcs_clear_all_stats()
306 mcs_clear_stats(mcs, MCS_FLOWID_STATS, id, dir); in mcs_clear_all_stats()
313 mcs_clear_stats(mcs, MCS_SECY_STATS, id, dir); in mcs_clear_all_stats()
320 mcs_clear_stats(mcs, MCS_SC_STATS, id, dir); in mcs_clear_all_stats()
327 mcs_clear_stats(mcs, MCS_SA_STATS, id, dir); in mcs_clear_all_stats()
332 void mcs_pn_table_write(struct mcs *mcs, u8 pn_id, u64 next_pn, u8 dir) in mcs_pn_table_write() argument
340 mcs_reg_write(mcs, reg, next_pn); in mcs_pn_table_write()
343 void cn10kb_mcs_tx_sa_mem_map_write(struct mcs *mcs, struct mcs_tx_sc_sa_map *map) in cn10kb_mcs_tx_sa_mem_map_write() argument
355 mcs_reg_write(mcs, reg, val); in cn10kb_mcs_tx_sa_mem_map_write()
359 mcs_reg_write(mcs, reg, val); in cn10kb_mcs_tx_sa_mem_map_write()
362 void cn10kb_mcs_rx_sa_mem_map_write(struct mcs *mcs, struct mcs_rx_sc_sa_map *map) in cn10kb_mcs_rx_sa_mem_map_write() argument
369 mcs_reg_write(mcs, reg, val); in cn10kb_mcs_rx_sa_mem_map_write()
372 void mcs_sa_plcy_write(struct mcs *mcs, u64 *plcy, int sa_id, int dir) in mcs_sa_plcy_write() argument
380 mcs_reg_write(mcs, reg, plcy[reg_id]); in mcs_sa_plcy_write()
385 mcs_reg_write(mcs, reg, plcy[reg_id]); in mcs_sa_plcy_write()
390 void mcs_ena_dis_sc_cam_entry(struct mcs *mcs, int sc_id, int ena) in mcs_ena_dis_sc_cam_entry() argument
399 val = mcs_reg_read(mcs, reg) | BIT_ULL(sc_id); in mcs_ena_dis_sc_cam_entry()
401 val = mcs_reg_read(mcs, reg) & ~BIT_ULL(sc_id); in mcs_ena_dis_sc_cam_entry()
403 mcs_reg_write(mcs, reg, val); in mcs_ena_dis_sc_cam_entry()
406 void mcs_rx_sc_cam_write(struct mcs *mcs, u64 sci, u64 secy, int sc_id) in mcs_rx_sc_cam_write() argument
408 mcs_reg_write(mcs, MCSX_CPM_RX_SLAVE_SC_CAMX(0, sc_id), sci); in mcs_rx_sc_cam_write()
409 mcs_reg_write(mcs, MCSX_CPM_RX_SLAVE_SC_CAMX(1, sc_id), secy); in mcs_rx_sc_cam_write()
411 mcs_ena_dis_sc_cam_entry(mcs, sc_id, true); in mcs_rx_sc_cam_write()
414 void mcs_secy_plcy_write(struct mcs *mcs, u64 plcy, int secy_id, int dir) in mcs_secy_plcy_write() argument
423 mcs_reg_write(mcs, reg, plcy); in mcs_secy_plcy_write()
425 if (mcs->hw->mcs_blks == 1 && dir == MCS_RX) in mcs_secy_plcy_write()
426 mcs_reg_write(mcs, MCSX_CPM_RX_SLAVE_SECY_PLCY_MEM_1X(secy_id), 0x0ull); in mcs_secy_plcy_write()
429 void cn10kb_mcs_flowid_secy_map(struct mcs *mcs, struct secy_mem_map *map, int dir) in cn10kb_mcs_flowid_secy_map() argument
441 mcs_reg_write(mcs, reg, val); in cn10kb_mcs_flowid_secy_map()
444 void mcs_ena_dis_flowid_entry(struct mcs *mcs, int flow_id, int dir, int ena) in mcs_ena_dis_flowid_entry() argument
460 val = mcs_reg_read(mcs, reg) | BIT_ULL(flow_id); in mcs_ena_dis_flowid_entry()
462 val = mcs_reg_read(mcs, reg) & ~BIT_ULL(flow_id); in mcs_ena_dis_flowid_entry()
464 mcs_reg_write(mcs, reg, val); in mcs_ena_dis_flowid_entry()
467 void mcs_flowid_entry_write(struct mcs *mcs, u64 *data, u64 *mask, int flow_id, int dir) in mcs_flowid_entry_write() argument
475 mcs_reg_write(mcs, reg, data[reg_id]); in mcs_flowid_entry_write()
477 mcs_reg_write(mcs, reg, mask[reg_id]); in mcs_flowid_entry_write()
482 mcs_reg_write(mcs, reg, data[reg_id]); in mcs_flowid_entry_write()
484 mcs_reg_write(mcs, reg, mask[reg_id]); in mcs_flowid_entry_write()
489 int mcs_install_flowid_bypass_entry(struct mcs *mcs) in mcs_install_flowid_bypass_entry() argument
496 flow_id = mcs->hw->tcam_entries - MCS_RSRC_RSVD_CNT; in mcs_install_flowid_bypass_entry()
499 mcs_reg_write(mcs, reg, GENMASK_ULL(63, 0)); in mcs_install_flowid_bypass_entry()
503 mcs_reg_write(mcs, reg, GENMASK_ULL(63, 0)); in mcs_install_flowid_bypass_entry()
506 secy_id = mcs->hw->secy_entries - MCS_RSRC_RSVD_CNT; in mcs_install_flowid_bypass_entry()
510 if (mcs->hw->mcs_blks > 1) in mcs_install_flowid_bypass_entry()
512 mcs_secy_plcy_write(mcs, plcy, secy_id, MCS_RX); in mcs_install_flowid_bypass_entry()
516 if (mcs->hw->mcs_blks > 1) in mcs_install_flowid_bypass_entry()
518 mcs_secy_plcy_write(mcs, plcy, secy_id, MCS_TX); in mcs_install_flowid_bypass_entry()
524 mcs->mcs_ops->mcs_flowid_secy_map(mcs, &map, MCS_RX); in mcs_install_flowid_bypass_entry()
526 mcs->mcs_ops->mcs_flowid_secy_map(mcs, &map, MCS_TX); in mcs_install_flowid_bypass_entry()
529 mcs_ena_dis_flowid_entry(mcs, flow_id, MCS_RX, true); in mcs_install_flowid_bypass_entry()
530 mcs_ena_dis_flowid_entry(mcs, flow_id, MCS_TX, true); in mcs_install_flowid_bypass_entry()
534 void mcs_clear_secy_plcy(struct mcs *mcs, int secy_id, int dir) in mcs_clear_secy_plcy() argument
540 map = &mcs->rx; in mcs_clear_secy_plcy()
542 map = &mcs->tx; in mcs_clear_secy_plcy()
545 mcs_secy_plcy_write(mcs, 0, secy_id, dir); in mcs_clear_secy_plcy()
551 mcs_ena_dis_flowid_entry(mcs, flow_id, dir, false); in mcs_clear_secy_plcy()
572 int mcs_free_ctrlpktrule(struct mcs *mcs, struct mcs_free_ctrl_pkt_rule_req *req) in mcs_free_ctrlpktrule() argument
580 map = (req->dir == MCS_RX) ? &mcs->rx : &mcs->tx; in mcs_free_ctrlpktrule()
587 dis = mcs_reg_read(mcs, reg); in mcs_free_ctrlpktrule()
589 mcs_reg_write(mcs, reg, dis); in mcs_free_ctrlpktrule()
595 dis = mcs_reg_read(mcs, reg); in mcs_free_ctrlpktrule()
597 mcs_reg_write(mcs, reg, dis); in mcs_free_ctrlpktrule()
602 int mcs_ctrlpktrule_write(struct mcs *mcs, struct mcs_ctrl_pkt_rule_write_req *req) in mcs_ctrlpktrule_write() argument
617 mcs_reg_write(mcs, reg, req->data0); in mcs_ctrlpktrule_write()
627 mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
636 mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
638 mcs_reg_write(mcs, reg, req->data1 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
641 mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
643 mcs_reg_write(mcs, reg, req->data1 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
655 mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
657 mcs_reg_write(mcs, reg, req->data1 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
659 mcs_reg_write(mcs, reg, req->data2); in mcs_ctrlpktrule_write()
662 mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
664 mcs_reg_write(mcs, reg, req->data1 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
666 mcs_reg_write(mcs, reg, req->data2); in mcs_ctrlpktrule_write()
677 mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
683 enb = mcs_reg_read(mcs, reg); in mcs_ctrlpktrule_write()
685 mcs_reg_write(mcs, reg, enb); in mcs_ctrlpktrule_write()
702 int mcs_free_all_rsrc(struct mcs *mcs, int dir, u16 pcifunc) in mcs_free_all_rsrc() argument
708 map = &mcs->rx; in mcs_free_all_rsrc()
710 map = &mcs->tx; in mcs_free_all_rsrc()
718 mcs_ena_dis_flowid_entry(mcs, id, dir, false); in mcs_free_all_rsrc()
727 mcs_clear_secy_plcy(mcs, id, dir); in mcs_free_all_rsrc()
738 mcs_ena_dis_sc_cam_entry(mcs, id, false); in mcs_free_all_rsrc()
761 int mcs_alloc_all_rsrc(struct mcs *mcs, u8 *flow_id, u8 *secy_id, in mcs_alloc_all_rsrc() argument
768 map = &mcs->rx; in mcs_alloc_all_rsrc()
770 map = &mcs->tx; in mcs_alloc_all_rsrc()
800 static void cn10kb_mcs_tx_pn_wrapped_handler(struct mcs *mcs) in cn10kb_mcs_tx_pn_wrapped_handler() argument
807 sc_bmap = &mcs->tx.sc; in cn10kb_mcs_tx_pn_wrapped_handler()
809 event.mcs_id = mcs->mcs_id; in cn10kb_mcs_tx_pn_wrapped_handler()
812 for_each_set_bit(sc, sc_bmap->bmap, mcs->hw->sc_entries) { in cn10kb_mcs_tx_pn_wrapped_handler()
813 val = mcs_reg_read(mcs, MCSX_CPM_TX_SLAVE_SA_MAP_MEM_0X(sc)); in cn10kb_mcs_tx_pn_wrapped_handler()
815 if (mcs->tx_sa_active[sc]) in cn10kb_mcs_tx_pn_wrapped_handler()
822 event.pcifunc = mcs->tx.sa2pf_map[event.sa_id]; in cn10kb_mcs_tx_pn_wrapped_handler()
823 mcs_add_intr_wq_entry(mcs, &event); in cn10kb_mcs_tx_pn_wrapped_handler()
827 static void cn10kb_mcs_tx_pn_thresh_reached_handler(struct mcs *mcs) in cn10kb_mcs_tx_pn_thresh_reached_handler() argument
834 sc_bmap = &mcs->tx.sc; in cn10kb_mcs_tx_pn_thresh_reached_handler()
836 event.mcs_id = mcs->mcs_id; in cn10kb_mcs_tx_pn_thresh_reached_handler()
844 for_each_set_bit(sc, sc_bmap->bmap, mcs->hw->sc_entries) { in cn10kb_mcs_tx_pn_thresh_reached_handler()
845 val = mcs_reg_read(mcs, MCSX_CPM_TX_SLAVE_SA_MAP_MEM_0X(sc)); in cn10kb_mcs_tx_pn_thresh_reached_handler()
853 if (status == mcs->tx_sa_active[sc]) in cn10kb_mcs_tx_pn_thresh_reached_handler()
861 event.pcifunc = mcs->tx.sa2pf_map[event.sa_id]; in cn10kb_mcs_tx_pn_thresh_reached_handler()
862 mcs_add_intr_wq_entry(mcs, &event); in cn10kb_mcs_tx_pn_thresh_reached_handler()
866 static void mcs_rx_pn_thresh_reached_handler(struct mcs *mcs) in mcs_rx_pn_thresh_reached_handler() argument
873 for (reg = 0; reg < (mcs->hw->sa_entries / 64); reg++) { in mcs_rx_pn_thresh_reached_handler()
877 intr = mcs_reg_read(mcs, MCSX_CPM_RX_SLAVE_PN_THRESH_REACHEDX(reg)); in mcs_rx_pn_thresh_reached_handler()
882 event.mcs_id = mcs->mcs_id; in mcs_rx_pn_thresh_reached_handler()
885 event.pcifunc = mcs->rx.sa2pf_map[event.sa_id]; in mcs_rx_pn_thresh_reached_handler()
886 mcs_add_intr_wq_entry(mcs, &event); in mcs_rx_pn_thresh_reached_handler()
891 static void mcs_rx_misc_intr_handler(struct mcs *mcs, u64 intr) in mcs_rx_misc_intr_handler() argument
895 event.mcs_id = mcs->mcs_id; in mcs_rx_misc_intr_handler()
896 event.pcifunc = mcs->pf_map[0]; in mcs_rx_misc_intr_handler()
911 mcs_add_intr_wq_entry(mcs, &event); in mcs_rx_misc_intr_handler()
914 static void mcs_tx_misc_intr_handler(struct mcs *mcs, u64 intr) in mcs_tx_misc_intr_handler() argument
921 event.mcs_id = mcs->mcs_id; in mcs_tx_misc_intr_handler()
922 event.pcifunc = mcs->pf_map[0]; in mcs_tx_misc_intr_handler()
926 mcs_add_intr_wq_entry(mcs, &event); in mcs_tx_misc_intr_handler()
929 static void mcs_bbe_intr_handler(struct mcs *mcs, u64 intr, enum mcs_direction dir) in mcs_bbe_intr_handler() argument
937 event.mcs_id = mcs->mcs_id; in mcs_bbe_intr_handler()
938 event.pcifunc = mcs->pf_map[0]; in mcs_bbe_intr_handler()
958 mcs_add_intr_wq_entry(mcs, &event); in mcs_bbe_intr_handler()
962 static void mcs_pab_intr_handler(struct mcs *mcs, u64 intr, enum mcs_direction dir) in mcs_pab_intr_handler() argument
970 event.mcs_id = mcs->mcs_id; in mcs_pab_intr_handler()
971 event.pcifunc = mcs->pf_map[0]; in mcs_pab_intr_handler()
982 mcs_add_intr_wq_entry(mcs, &event); in mcs_pab_intr_handler()
988 struct mcs *mcs = (struct mcs *)mcs_irq; in mcs_ip_intr_handler() local
992 mcs_reg_write(mcs, MCSX_IP_INT_ENA_W1C, BIT_ULL(0)); in mcs_ip_intr_handler()
993 mcs_reg_write(mcs, MCSX_IP_INT, BIT_ULL(0)); in mcs_ip_intr_handler()
996 intr = mcs_reg_read(mcs, MCSX_TOP_SLAVE_INT_SUM); in mcs_ip_intr_handler()
1001 cpm_intr = mcs_reg_read(mcs, MCSX_CPM_RX_SLAVE_RX_INT); in mcs_ip_intr_handler()
1004 mcs_rx_pn_thresh_reached_handler(mcs); in mcs_ip_intr_handler()
1007 mcs_rx_misc_intr_handler(mcs, cpm_intr); in mcs_ip_intr_handler()
1010 mcs_reg_write(mcs, MCSX_CPM_RX_SLAVE_RX_INT, cpm_intr); in mcs_ip_intr_handler()
1015 cpm_intr = mcs_reg_read(mcs, MCSX_CPM_TX_SLAVE_TX_INT); in mcs_ip_intr_handler()
1018 if (mcs->hw->mcs_blks > 1) in mcs_ip_intr_handler()
1019 cnf10kb_mcs_tx_pn_thresh_reached_handler(mcs); in mcs_ip_intr_handler()
1021 cn10kb_mcs_tx_pn_thresh_reached_handler(mcs); in mcs_ip_intr_handler()
1025 mcs_tx_misc_intr_handler(mcs, cpm_intr); in mcs_ip_intr_handler()
1028 if (mcs->hw->mcs_blks > 1) in mcs_ip_intr_handler()
1029 cnf10kb_mcs_tx_pn_wrapped_handler(mcs); in mcs_ip_intr_handler()
1031 cn10kb_mcs_tx_pn_wrapped_handler(mcs); in mcs_ip_intr_handler()
1034 mcs_reg_write(mcs, MCSX_CPM_TX_SLAVE_TX_INT, cpm_intr); in mcs_ip_intr_handler()
1039 bbe_intr = mcs_reg_read(mcs, MCSX_BBE_RX_SLAVE_BBE_INT); in mcs_ip_intr_handler()
1040 mcs_bbe_intr_handler(mcs, bbe_intr, MCS_RX); in mcs_ip_intr_handler()
1043 mcs_reg_write(mcs, MCSX_BBE_RX_SLAVE_BBE_INT_INTR_RW, 0); in mcs_ip_intr_handler()
1044 mcs_reg_write(mcs, MCSX_BBE_RX_SLAVE_BBE_INT, bbe_intr); in mcs_ip_intr_handler()
1049 bbe_intr = mcs_reg_read(mcs, MCSX_BBE_TX_SLAVE_BBE_INT); in mcs_ip_intr_handler()
1050 mcs_bbe_intr_handler(mcs, bbe_intr, MCS_TX); in mcs_ip_intr_handler()
1053 mcs_reg_write(mcs, MCSX_BBE_TX_SLAVE_BBE_INT_INTR_RW, 0); in mcs_ip_intr_handler()
1054 mcs_reg_write(mcs, MCSX_BBE_TX_SLAVE_BBE_INT, bbe_intr); in mcs_ip_intr_handler()
1059 pab_intr = mcs_reg_read(mcs, MCSX_PAB_RX_SLAVE_PAB_INT); in mcs_ip_intr_handler()
1060 mcs_pab_intr_handler(mcs, pab_intr, MCS_RX); in mcs_ip_intr_handler()
1063 mcs_reg_write(mcs, MCSX_PAB_RX_SLAVE_PAB_INT_INTR_RW, 0); in mcs_ip_intr_handler()
1064 mcs_reg_write(mcs, MCSX_PAB_RX_SLAVE_PAB_INT, pab_intr); in mcs_ip_intr_handler()
1069 pab_intr = mcs_reg_read(mcs, MCSX_PAB_TX_SLAVE_PAB_INT); in mcs_ip_intr_handler()
1070 mcs_pab_intr_handler(mcs, pab_intr, MCS_TX); in mcs_ip_intr_handler()
1073 mcs_reg_write(mcs, MCSX_PAB_TX_SLAVE_PAB_INT_INTR_RW, 0); in mcs_ip_intr_handler()
1074 mcs_reg_write(mcs, MCSX_PAB_TX_SLAVE_PAB_INT, pab_intr); in mcs_ip_intr_handler()
1078 mcs_reg_write(mcs, MCSX_IP_INT_ENA_W1S, BIT_ULL(0)); in mcs_ip_intr_handler()
1083 static void *alloc_mem(struct mcs *mcs, int n) in alloc_mem() argument
1085 return devm_kcalloc(mcs->dev, n, sizeof(u16), GFP_KERNEL); in alloc_mem()
1088 static int mcs_alloc_struct_mem(struct mcs *mcs, struct mcs_rsrc_map *res) in mcs_alloc_struct_mem() argument
1090 struct hwinfo *hw = mcs->hw; in mcs_alloc_struct_mem()
1093 res->flowid2pf_map = alloc_mem(mcs, hw->tcam_entries); in mcs_alloc_struct_mem()
1097 res->secy2pf_map = alloc_mem(mcs, hw->secy_entries); in mcs_alloc_struct_mem()
1101 res->sc2pf_map = alloc_mem(mcs, hw->sc_entries); in mcs_alloc_struct_mem()
1105 res->sa2pf_map = alloc_mem(mcs, hw->sa_entries); in mcs_alloc_struct_mem()
1109 res->flowid2secy_map = alloc_mem(mcs, hw->tcam_entries); in mcs_alloc_struct_mem()
1113 res->ctrlpktrule2pf_map = alloc_mem(mcs, MCS_MAX_CTRLPKT_RULES); in mcs_alloc_struct_mem()
1145 static int mcs_register_interrupts(struct mcs *mcs) in mcs_register_interrupts() argument
1149 mcs->num_vec = pci_msix_vec_count(mcs->pdev); in mcs_register_interrupts()
1151 ret = pci_alloc_irq_vectors(mcs->pdev, mcs->num_vec, in mcs_register_interrupts()
1152 mcs->num_vec, PCI_IRQ_MSIX); in mcs_register_interrupts()
1154 dev_err(mcs->dev, "MCS Request for %d msix vector failed err:%d\n", in mcs_register_interrupts()
1155 mcs->num_vec, ret); in mcs_register_interrupts()
1159 ret = request_irq(pci_irq_vector(mcs->pdev, MCS_INT_VEC_IP), in mcs_register_interrupts()
1160 mcs_ip_intr_handler, 0, "MCS_IP", mcs); in mcs_register_interrupts()
1162 dev_err(mcs->dev, "MCS IP irq registration failed\n"); in mcs_register_interrupts()
1167 mcs_reg_write(mcs, MCSX_IP_INT_ENA_W1S, BIT_ULL(0)); in mcs_register_interrupts()
1170 mcs_reg_write(mcs, MCSX_TOP_SLAVE_INT_SUM_ENB, in mcs_register_interrupts()
1175 mcs_reg_write(mcs, MCSX_CPM_TX_SLAVE_TX_INT_ENB, 0x7ULL); in mcs_register_interrupts()
1176 mcs_reg_write(mcs, MCSX_CPM_RX_SLAVE_RX_INT_ENB, 0x7FULL); in mcs_register_interrupts()
1178 mcs_reg_write(mcs, MCSX_BBE_RX_SLAVE_BBE_INT_ENB, 0xff); in mcs_register_interrupts()
1179 mcs_reg_write(mcs, MCSX_BBE_TX_SLAVE_BBE_INT_ENB, 0xff); in mcs_register_interrupts()
1181 mcs_reg_write(mcs, MCSX_PAB_RX_SLAVE_PAB_INT_ENB, 0xff); in mcs_register_interrupts()
1182 mcs_reg_write(mcs, MCSX_PAB_TX_SLAVE_PAB_INT_ENB, 0xff); in mcs_register_interrupts()
1184 mcs->tx_sa_active = alloc_mem(mcs, mcs->hw->sc_entries); in mcs_register_interrupts()
1185 if (!mcs->tx_sa_active) { in mcs_register_interrupts()
1193 free_irq(pci_irq_vector(mcs->pdev, MCS_INT_VEC_IP), mcs); in mcs_register_interrupts()
1195 pci_free_irq_vectors(mcs->pdev); in mcs_register_interrupts()
1196 mcs->num_vec = 0; in mcs_register_interrupts()
1202 struct mcs *mcs; in mcs_get_blkcnt() local
1209 list_for_each_entry(mcs, &mcs_list, mcs_list) in mcs_get_blkcnt()
1210 if (mcs->mcs_id > idmax) in mcs_get_blkcnt()
1211 idmax = mcs->mcs_id; in mcs_get_blkcnt()
1219 struct mcs *mcs_get_pdata(int mcs_id) in mcs_get_pdata()
1221 struct mcs *mcs_dev; in mcs_get_pdata()
1230 void mcs_set_port_cfg(struct mcs *mcs, struct mcs_port_cfg_set_req *req) in mcs_set_port_cfg() argument
1234 mcs_reg_write(mcs, MCSX_PAB_RX_SLAVE_PORT_CFGX(req->port_id), in mcs_set_port_cfg()
1239 if (mcs->hw->mcs_blks > 1) { in mcs_set_port_cfg()
1243 mcs_reg_write(mcs, MCSX_PAB_RX_SLAVE_FIFO_SKID_CFGX(req->port_id), val); in mcs_set_port_cfg()
1244 mcs_reg_write(mcs, MCSX_PEX_TX_SLAVE_CUSTOM_TAG_REL_MODE_SEL(req->port_id), in mcs_set_port_cfg()
1246 val = mcs_reg_read(mcs, MCSX_PEX_RX_SLAVE_PEX_CONFIGURATION); in mcs_set_port_cfg()
1253 mcs_reg_write(mcs, MCSX_PEX_RX_SLAVE_PEX_CONFIGURATION, val); in mcs_set_port_cfg()
1255 val = mcs_reg_read(mcs, MCSX_PEX_TX_SLAVE_PORT_CONFIG(req->port_id)); in mcs_set_port_cfg()
1257 mcs_reg_write(mcs, MCSX_PEX_TX_SLAVE_PORT_CONFIG(req->port_id), val); in mcs_set_port_cfg()
1261 void mcs_get_port_cfg(struct mcs *mcs, struct mcs_port_cfg_get_req *req, in mcs_get_port_cfg() argument
1266 rsp->port_mode = mcs_reg_read(mcs, MCSX_PAB_RX_SLAVE_PORT_CFGX(req->port_id)) & in mcs_get_port_cfg()
1269 if (mcs->hw->mcs_blks > 1) { in mcs_get_port_cfg()
1271 rsp->fifo_skid = mcs_reg_read(mcs, reg) & MCS_PORT_FIFO_SKID_MASK; in mcs_get_port_cfg()
1273 rsp->cstm_tag_rel_mode_sel = mcs_reg_read(mcs, reg) & 0x3; in mcs_get_port_cfg()
1274 if (mcs_reg_read(mcs, MCSX_PEX_RX_SLAVE_PEX_CONFIGURATION) & BIT_ULL(req->port_id)) in mcs_get_port_cfg()
1278 rsp->cstm_tag_rel_mode_sel = mcs_reg_read(mcs, reg) >> 2; in mcs_get_port_cfg()
1285 void mcs_get_custom_tag_cfg(struct mcs *mcs, struct mcs_custom_tag_cfg_get_req *req, in mcs_get_custom_tag_cfg() argument
1292 if (mcs->hw->mcs_blks > 1) in mcs_get_custom_tag_cfg()
1299 val = mcs_reg_read(mcs, reg); in mcs_get_custom_tag_cfg()
1300 if (mcs->hw->mcs_blks > 1) { in mcs_get_custom_tag_cfg()
1305 rsp->cstm_etype_en = mcs_reg_read(mcs, reg) & 0xFF; in mcs_get_custom_tag_cfg()
1317 void mcs_reset_port(struct mcs *mcs, u8 port_id, u8 reset) in mcs_reset_port() argument
1321 mcs_reg_write(mcs, reg, reset & 0x1); in mcs_reset_port()
1325 void mcs_set_lmac_mode(struct mcs *mcs, int lmac_id, u8 mode) in mcs_set_lmac_mode() argument
1330 mcs_reg_write(mcs, reg, (u64)mode); in mcs_set_lmac_mode()
1333 void mcs_pn_threshold_set(struct mcs *mcs, struct mcs_set_pn_threshold *pn) in mcs_pn_threshold_set() argument
1342 mcs_reg_write(mcs, reg, pn->threshold); in mcs_pn_threshold_set()
1345 void cn10kb_mcs_parser_cfg(struct mcs *mcs) in cn10kb_mcs_parser_cfg() argument
1353 mcs_reg_write(mcs, reg, val); in cn10kb_mcs_parser_cfg()
1357 mcs_reg_write(mcs, reg, val); in cn10kb_mcs_parser_cfg()
1363 mcs_reg_write(mcs, reg, val); in cn10kb_mcs_parser_cfg()
1367 mcs_reg_write(mcs, reg, val); in cn10kb_mcs_parser_cfg()
1370 static void mcs_lmac_init(struct mcs *mcs, int lmac_id) in mcs_lmac_init() argument
1376 mcs_reg_write(mcs, reg, 0); in mcs_lmac_init()
1378 if (mcs->hw->mcs_blks > 1) { in mcs_lmac_init()
1380 mcs_reg_write(mcs, reg, 0xe000e); in mcs_lmac_init()
1385 mcs_reg_write(mcs, reg, 0); in mcs_lmac_init()
1390 struct mcs *mcs; in mcs_set_lmac_channels() local
1394 mcs = mcs_get_pdata(mcs_id); in mcs_set_lmac_channels()
1395 if (!mcs) in mcs_set_lmac_channels()
1397 for (lmac = 0; lmac < mcs->hw->lmac_cnt; lmac++) { in mcs_set_lmac_channels()
1398 cfg = mcs_reg_read(mcs, MCSX_LINK_LMACX_CFG(lmac)); in mcs_set_lmac_channels()
1402 mcs_reg_write(mcs, MCSX_LINK_LMACX_CFG(lmac), cfg); in mcs_set_lmac_channels()
1408 static int mcs_x2p_calibration(struct mcs *mcs) in mcs_x2p_calibration() argument
1415 val = mcs_reg_read(mcs, MCSX_MIL_GLOBAL); in mcs_x2p_calibration()
1417 mcs_reg_write(mcs, MCSX_MIL_GLOBAL, val); in mcs_x2p_calibration()
1420 while (!(mcs_reg_read(mcs, MCSX_MIL_RX_GBL_STATUS) & BIT_ULL(0))) { in mcs_x2p_calibration()
1426 dev_err(mcs->dev, "MCS X2P calibration failed..ignoring\n"); in mcs_x2p_calibration()
1431 val = mcs_reg_read(mcs, MCSX_MIL_RX_GBL_STATUS); in mcs_x2p_calibration()
1432 for (i = 0; i < mcs->hw->mcs_x2p_intf; i++) { in mcs_x2p_calibration()
1436 dev_err(mcs->dev, "MCS:%d didn't respond to X2P calibration\n", i); in mcs_x2p_calibration()
1439 mcs_reg_write(mcs, MCSX_MIL_GLOBAL, mcs_reg_read(mcs, MCSX_MIL_GLOBAL) & ~BIT_ULL(5)); in mcs_x2p_calibration()
1444 static void mcs_set_external_bypass(struct mcs *mcs, u8 bypass) in mcs_set_external_bypass() argument
1449 val = mcs_reg_read(mcs, MCSX_MIL_GLOBAL); in mcs_set_external_bypass()
1454 mcs_reg_write(mcs, MCSX_MIL_GLOBAL, val); in mcs_set_external_bypass()
1457 static void mcs_global_cfg(struct mcs *mcs) in mcs_global_cfg() argument
1460 mcs_set_external_bypass(mcs, false); in mcs_global_cfg()
1463 mcs_reg_write(mcs, MCSX_CSE_RX_SLAVE_STATS_CLEAR, 0x1F); in mcs_global_cfg()
1464 mcs_reg_write(mcs, MCSX_CSE_TX_SLAVE_STATS_CLEAR, 0x1F); in mcs_global_cfg()
1467 if (mcs->hw->mcs_blks == 1) { in mcs_global_cfg()
1468 mcs_reg_write(mcs, MCSX_IP_MODE, BIT_ULL(3)); in mcs_global_cfg()
1472 mcs_reg_write(mcs, MCSX_BBE_RX_SLAVE_CAL_ENTRY, 0xe4); in mcs_global_cfg()
1473 mcs_reg_write(mcs, MCSX_BBE_RX_SLAVE_CAL_LEN, 4); in mcs_global_cfg()
1476 void cn10kb_mcs_set_hw_capabilities(struct mcs *mcs) in cn10kb_mcs_set_hw_capabilities() argument
1478 struct hwinfo *hw = mcs->hw; in cn10kb_mcs_set_hw_capabilities()
1501 struct mcs *mcs; in mcs_probe() local
1503 mcs = devm_kzalloc(dev, sizeof(*mcs), GFP_KERNEL); in mcs_probe()
1504 if (!mcs) in mcs_probe()
1507 mcs->hw = devm_kzalloc(dev, sizeof(struct hwinfo), GFP_KERNEL); in mcs_probe()
1508 if (!mcs->hw) in mcs_probe()
1524 mcs->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); in mcs_probe()
1525 if (!mcs->reg_base) { in mcs_probe()
1531 pci_set_drvdata(pdev, mcs); in mcs_probe()
1532 mcs->pdev = pdev; in mcs_probe()
1533 mcs->dev = &pdev->dev; in mcs_probe()
1536 mcs->mcs_ops = &cn10kb_mcs_ops; in mcs_probe()
1538 mcs->mcs_ops = cnf10kb_get_mac_ops(); in mcs_probe()
1541 mcs->mcs_ops->mcs_set_hw_capabilities(mcs); in mcs_probe()
1543 mcs_global_cfg(mcs); in mcs_probe()
1546 err = mcs_x2p_calibration(mcs); in mcs_probe()
1550 mcs->mcs_id = (pci_resource_start(pdev, PCI_CFG_REG_BAR_NUM) >> 24) in mcs_probe()
1554 err = mcs_alloc_struct_mem(mcs, &mcs->tx); in mcs_probe()
1559 err = mcs_alloc_struct_mem(mcs, &mcs->rx); in mcs_probe()
1564 for (lmac = 0; lmac < mcs->hw->lmac_cnt; lmac++) in mcs_probe()
1565 mcs_lmac_init(mcs, lmac); in mcs_probe()
1568 mcs->mcs_ops->mcs_parser_cfg(mcs); in mcs_probe()
1570 err = mcs_register_interrupts(mcs); in mcs_probe()
1574 list_add(&mcs->mcs_list, &mcs_list); in mcs_probe()
1575 mutex_init(&mcs->stats_lock); in mcs_probe()
1581 mcs_set_external_bypass(mcs, true); in mcs_probe()
1591 struct mcs *mcs = pci_get_drvdata(pdev); in mcs_remove() local
1594 mcs_set_external_bypass(mcs, true); in mcs_remove()
1595 free_irq(pci_irq_vector(pdev, MCS_INT_VEC_IP), mcs); in mcs_remove()