Lines Matching refs:mcs
23 void cnf10kb_mcs_set_hw_capabilities(struct mcs *mcs) in cnf10kb_mcs_set_hw_capabilities() argument
25 struct hwinfo *hw = mcs->hw; in cnf10kb_mcs_set_hw_capabilities()
36 void cnf10kb_mcs_parser_cfg(struct mcs *mcs) in cnf10kb_mcs_parser_cfg() argument
44 mcs_reg_write(mcs, reg, val); in cnf10kb_mcs_parser_cfg()
47 mcs_reg_write(mcs, reg, val); in cnf10kb_mcs_parser_cfg()
54 mcs_reg_write(mcs, reg, val); in cnf10kb_mcs_parser_cfg()
58 mcs_reg_write(mcs, reg, val); in cnf10kb_mcs_parser_cfg()
64 mcs_reg_write(mcs, reg, val); in cnf10kb_mcs_parser_cfg()
67 mcs_reg_write(mcs, reg, val); in cnf10kb_mcs_parser_cfg()
70 void cnf10kb_mcs_flowid_secy_map(struct mcs *mcs, struct secy_mem_map *map, int dir) in cnf10kb_mcs_flowid_secy_map() argument
79 mcs_reg_write(mcs, reg, map->sci); in cnf10kb_mcs_flowid_secy_map()
84 mcs_reg_write(mcs, reg, val); in cnf10kb_mcs_flowid_secy_map()
87 void cnf10kb_mcs_tx_sa_mem_map_write(struct mcs *mcs, struct mcs_tx_sc_sa_map *map) in cnf10kb_mcs_tx_sa_mem_map_write() argument
94 mcs_reg_write(mcs, reg, val); in cnf10kb_mcs_tx_sa_mem_map_write()
97 val = mcs_reg_read(mcs, reg); in cnf10kb_mcs_tx_sa_mem_map_write()
104 mcs_reg_write(mcs, reg, val); in cnf10kb_mcs_tx_sa_mem_map_write()
106 mcs_reg_write(mcs, MCSX_CPM_TX_SLAVE_SA_INDEX0_VLDX(map->sc_id), map->sa_index0_vld); in cnf10kb_mcs_tx_sa_mem_map_write()
107 mcs_reg_write(mcs, MCSX_CPM_TX_SLAVE_SA_INDEX1_VLDX(map->sc_id), map->sa_index1_vld); in cnf10kb_mcs_tx_sa_mem_map_write()
109 mcs_reg_write(mcs, MCSX_CPM_TX_SLAVE_TX_SA_ACTIVEX(map->sc_id), map->tx_sa_active); in cnf10kb_mcs_tx_sa_mem_map_write()
112 void cnf10kb_mcs_rx_sa_mem_map_write(struct mcs *mcs, struct mcs_rx_sc_sa_map *map) in cnf10kb_mcs_rx_sa_mem_map_write() argument
119 mcs_reg_write(mcs, reg, val); in cnf10kb_mcs_rx_sa_mem_map_write()
122 int mcs_set_force_clk_en(struct mcs *mcs, bool set) in mcs_set_force_clk_en() argument
127 val = mcs_reg_read(mcs, MCSX_MIL_GLOBAL); in mcs_set_force_clk_en()
131 mcs_reg_write(mcs, MCSX_MIL_GLOBAL, val); in mcs_set_force_clk_en()
134 while (!(mcs_reg_read(mcs, MCSX_MIL_IP_GBL_STATUS) & BIT_ULL(0))) { in mcs_set_force_clk_en()
136 dev_err(mcs->dev, "MCS set force clk enable failed\n"); in mcs_set_force_clk_en()
142 mcs_reg_write(mcs, MCSX_MIL_GLOBAL, val); in mcs_set_force_clk_en()
153 void cnf10kb_mcs_tx_pn_thresh_reached_handler(struct mcs *mcs) in cnf10kb_mcs_tx_pn_thresh_reached_handler() argument
161 sc_bmap = &mcs->tx.sc; in cnf10kb_mcs_tx_pn_thresh_reached_handler()
163 event.mcs_id = mcs->mcs_id; in cnf10kb_mcs_tx_pn_thresh_reached_handler()
166 rekey_ena = mcs_reg_read(mcs, MCSX_CPM_TX_SLAVE_AUTO_REKEY_ENABLE_0); in cnf10kb_mcs_tx_pn_thresh_reached_handler()
168 for_each_set_bit(sc, sc_bmap->bmap, mcs->hw->sc_entries) { in cnf10kb_mcs_tx_pn_thresh_reached_handler()
172 sa_status = mcs_reg_read(mcs, MCSX_CPM_TX_SLAVE_TX_SA_ACTIVEX(sc)); in cnf10kb_mcs_tx_pn_thresh_reached_handler()
174 if (sa_status == mcs->tx_sa_active[sc]) in cnf10kb_mcs_tx_pn_thresh_reached_handler()
178 val = mcs_reg_read(mcs, MCSX_CPM_TX_SLAVE_SA_MAP_MEM_0X(sc)); in cnf10kb_mcs_tx_pn_thresh_reached_handler()
184 event.pcifunc = mcs->tx.sa2pf_map[event.sa_id]; in cnf10kb_mcs_tx_pn_thresh_reached_handler()
185 mcs_add_intr_wq_entry(mcs, &event); in cnf10kb_mcs_tx_pn_thresh_reached_handler()
189 void cnf10kb_mcs_tx_pn_wrapped_handler(struct mcs *mcs) in cnf10kb_mcs_tx_pn_wrapped_handler() argument
196 sc_bmap = &mcs->tx.sc; in cnf10kb_mcs_tx_pn_wrapped_handler()
198 event.mcs_id = mcs->mcs_id; in cnf10kb_mcs_tx_pn_wrapped_handler()
201 for_each_set_bit(sc, sc_bmap->bmap, mcs->hw->sc_entries) { in cnf10kb_mcs_tx_pn_wrapped_handler()
202 val = mcs_reg_read(mcs, MCSX_CPM_TX_SLAVE_SA_MAP_MEM_0X(sc)); in cnf10kb_mcs_tx_pn_wrapped_handler()
204 if (mcs->tx_sa_active[sc]) in cnf10kb_mcs_tx_pn_wrapped_handler()
211 event.pcifunc = mcs->tx.sa2pf_map[event.sa_id]; in cnf10kb_mcs_tx_pn_wrapped_handler()
212 mcs_add_intr_wq_entry(mcs, &event); in cnf10kb_mcs_tx_pn_wrapped_handler()