Lines Matching refs:rvu
15 static int npa_aq_enqueue_wait(struct rvu *rvu, struct rvu_block *block, in npa_aq_enqueue_wait() argument
26 reg = rvu_read64(rvu, block->addr, NPA_AF_AQ_STATUS); in npa_aq_enqueue_wait()
36 rvu_write64(rvu, block->addr, NPA_AF_AQ_DOOR, 1); in npa_aq_enqueue_wait()
50 if (rvu_ndc_fix_locked_cacheline(rvu, BLKADDR_NDC_NPA0)) in npa_aq_enqueue_wait()
51 dev_err(rvu->dev, in npa_aq_enqueue_wait()
61 int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_enq_req *req, in rvu_npa_aq_enq_inst() argument
64 struct rvu_hwinfo *hw = rvu->hw; in rvu_npa_aq_enq_inst()
74 pfvf = rvu_get_pfvf(rvu, pcifunc); in rvu_npa_aq_enq_inst()
78 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPA, pcifunc); in rvu_npa_aq_enq_inst()
85 dev_warn(rvu->dev, "%s: NPA AQ not initialized\n", __func__); in rvu_npa_aq_enq_inst()
89 npalf = rvu_get_lf(rvu, block, pcifunc, 0); in rvu_npa_aq_enq_inst()
158 rc = npa_aq_enqueue_wait(rvu, block, &inst); in rvu_npa_aq_enq_inst()
210 static int npa_lf_hwctx_disable(struct rvu *rvu, struct hwctx_disable_req *req) in npa_lf_hwctx_disable() argument
212 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, req->hdr.pcifunc); in npa_lf_hwctx_disable()
245 rc = rvu_npa_aq_enq_inst(rvu, &aq_req, NULL); in npa_lf_hwctx_disable()
248 dev_err(rvu->dev, "Failed to disable %s:%d context\n", in npa_lf_hwctx_disable()
258 static int npa_lf_hwctx_lockdown(struct rvu *rvu, struct npa_aq_enq_req *req) in npa_lf_hwctx_lockdown() argument
271 err = rvu_npa_aq_enq_inst(rvu, &lock_ctx_req, NULL); in npa_lf_hwctx_lockdown()
273 dev_err(rvu->dev, in npa_lf_hwctx_lockdown()
281 int rvu_mbox_handler_npa_aq_enq(struct rvu *rvu, in rvu_mbox_handler_npa_aq_enq() argument
287 err = rvu_npa_aq_enq_inst(rvu, req, rsp); in rvu_mbox_handler_npa_aq_enq()
289 err = npa_lf_hwctx_lockdown(rvu, req); in rvu_mbox_handler_npa_aq_enq()
294 int rvu_mbox_handler_npa_aq_enq(struct rvu *rvu, in rvu_mbox_handler_npa_aq_enq() argument
298 return rvu_npa_aq_enq_inst(rvu, req, rsp); in rvu_mbox_handler_npa_aq_enq()
302 int rvu_mbox_handler_npa_hwctx_disable(struct rvu *rvu, in rvu_mbox_handler_npa_hwctx_disable() argument
306 return npa_lf_hwctx_disable(rvu, req); in rvu_mbox_handler_npa_hwctx_disable()
309 static void npa_ctx_free(struct rvu *rvu, struct rvu_pfvf *pfvf) in npa_ctx_free() argument
314 qmem_free(rvu->dev, pfvf->aura_ctx); in npa_ctx_free()
320 qmem_free(rvu->dev, pfvf->pool_ctx); in npa_ctx_free()
323 qmem_free(rvu->dev, pfvf->npa_qints_ctx); in npa_ctx_free()
327 int rvu_mbox_handler_npa_lf_alloc(struct rvu *rvu, in rvu_mbox_handler_npa_lf_alloc() argument
332 struct rvu_hwinfo *hw = rvu->hw; in rvu_mbox_handler_npa_lf_alloc()
346 pfvf = rvu_get_pfvf(rvu, pcifunc); in rvu_mbox_handler_npa_lf_alloc()
347 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPA, pcifunc); in rvu_mbox_handler_npa_lf_alloc()
352 npalf = rvu_get_lf(rvu, block, pcifunc, 0); in rvu_mbox_handler_npa_lf_alloc()
357 err = rvu_lf_reset(rvu, block, npalf); in rvu_mbox_handler_npa_lf_alloc()
359 dev_err(rvu->dev, "Failed to reset NPALF%d\n", npalf); in rvu_mbox_handler_npa_lf_alloc()
363 ctx_cfg = rvu_read64(rvu, blkaddr, NPA_AF_CONST1); in rvu_mbox_handler_npa_lf_alloc()
367 err = qmem_alloc(rvu->dev, &pfvf->aura_ctx, in rvu_mbox_handler_npa_lf_alloc()
379 err = qmem_alloc(rvu->dev, &pfvf->pool_ctx, req->nr_pools, hwctx_size); in rvu_mbox_handler_npa_lf_alloc()
389 cfg = rvu_read64(rvu, blkaddr, NPA_AF_CONST); in rvu_mbox_handler_npa_lf_alloc()
394 err = qmem_alloc(rvu->dev, &pfvf->npa_qints_ctx, qints, hwctx_size); in rvu_mbox_handler_npa_lf_alloc()
398 cfg = rvu_read64(rvu, blkaddr, NPA_AF_LFX_AURAS_CFG(npalf)); in rvu_mbox_handler_npa_lf_alloc()
404 rvu_write64(rvu, blkaddr, NPA_AF_LFX_AURAS_CFG(npalf), cfg); in rvu_mbox_handler_npa_lf_alloc()
407 rvu_write64(rvu, blkaddr, NPA_AF_LFX_LOC_AURAS_BASE(npalf), in rvu_mbox_handler_npa_lf_alloc()
411 rvu_write64(rvu, blkaddr, NPA_AF_LFX_QINTS_CFG(npalf), in rvu_mbox_handler_npa_lf_alloc()
413 rvu_write64(rvu, blkaddr, NPA_AF_LFX_QINTS_BASE(npalf), in rvu_mbox_handler_npa_lf_alloc()
419 npa_ctx_free(rvu, pfvf); in rvu_mbox_handler_npa_lf_alloc()
424 cfg = rvu_read64(rvu, blkaddr, NPA_AF_CONST); in rvu_mbox_handler_npa_lf_alloc()
428 if (!is_rvu_otx2(rvu)) { in rvu_mbox_handler_npa_lf_alloc()
429 cfg = rvu_read64(rvu, block->addr, NPA_AF_BATCH_CTL); in rvu_mbox_handler_npa_lf_alloc()
435 int rvu_mbox_handler_npa_lf_free(struct rvu *rvu, struct msg_req *req, in rvu_mbox_handler_npa_lf_free() argument
438 struct rvu_hwinfo *hw = rvu->hw; in rvu_mbox_handler_npa_lf_free()
445 pfvf = rvu_get_pfvf(rvu, pcifunc); in rvu_mbox_handler_npa_lf_free()
446 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPA, pcifunc); in rvu_mbox_handler_npa_lf_free()
451 npalf = rvu_get_lf(rvu, block, pcifunc, 0); in rvu_mbox_handler_npa_lf_free()
456 err = rvu_lf_reset(rvu, block, npalf); in rvu_mbox_handler_npa_lf_free()
458 dev_err(rvu->dev, "Failed to reset NPALF%d\n", npalf); in rvu_mbox_handler_npa_lf_free()
462 npa_ctx_free(rvu, pfvf); in rvu_mbox_handler_npa_lf_free()
467 static int npa_aq_init(struct rvu *rvu, struct rvu_block *block) in npa_aq_init() argument
473 cfg = rvu_read64(rvu, block->addr, NPA_AF_GEN_CFG); in npa_aq_init()
476 rvu_write64(rvu, block->addr, NPA_AF_GEN_CFG, cfg); in npa_aq_init()
479 rvu_write64(rvu, block->addr, NPA_AF_GEN_CFG, cfg); in npa_aq_init()
483 cfg = rvu_read64(rvu, block->addr, NPA_AF_NDC_CFG); in npa_aq_init()
489 rvu_write64(rvu, block->addr, NPA_AF_NDC_CFG, cfg); in npa_aq_init()
492 if (!is_rvu_otx2(rvu)) { in npa_aq_init()
493 cfg = rvu_read64(rvu, block->addr, NPA_AF_BATCH_CTL); in npa_aq_init()
496 rvu_write64(rvu, block->addr, NPA_AF_BATCH_CTL, cfg); in npa_aq_init()
502 err = rvu_aq_alloc(rvu, &block->aq, in npa_aq_init()
508 rvu_write64(rvu, block->addr, NPA_AF_AQ_CFG, AQ_SIZE); in npa_aq_init()
509 rvu_write64(rvu, block->addr, in npa_aq_init()
514 int rvu_npa_init(struct rvu *rvu) in rvu_npa_init() argument
516 struct rvu_hwinfo *hw = rvu->hw; in rvu_npa_init()
519 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPA, 0); in rvu_npa_init()
524 return npa_aq_init(rvu, &hw->block[blkaddr]); in rvu_npa_init()
527 void rvu_npa_freemem(struct rvu *rvu) in rvu_npa_freemem() argument
529 struct rvu_hwinfo *hw = rvu->hw; in rvu_npa_freemem()
533 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPA, 0); in rvu_npa_freemem()
538 rvu_aq_free(rvu, block->aq); in rvu_npa_freemem()
541 void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, int npalf) in rvu_npa_lf_teardown() argument
543 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); in rvu_npa_lf_teardown()
549 npa_lf_hwctx_disable(rvu, &ctx_req); in rvu_npa_lf_teardown()
553 npa_lf_hwctx_disable(rvu, &ctx_req); in rvu_npa_lf_teardown()
555 npa_ctx_free(rvu, pfvf); in rvu_npa_lf_teardown()
565 int rvu_ndc_fix_locked_cacheline(struct rvu *rvu, int blkaddr) in rvu_ndc_fix_locked_cacheline() argument
571 reg = rvu_read64(rvu, blkaddr, NDC_AF_CAMS_RD_INTERVAL); in rvu_ndc_fix_locked_cacheline()
572 rvu_write64(rvu, blkaddr, NDC_AF_CAMS_RD_INTERVAL, reg & GENMASK_ULL(62, 0)); in rvu_ndc_fix_locked_cacheline()
575 err = rvu_poll_reg(rvu, blkaddr, NDC_AF_CAMS_RD_INTERVAL, GENMASK_ULL(47, 32), true); in rvu_ndc_fix_locked_cacheline()
577 dev_err(rvu->dev, "Timed out while polling for NDC CAM busy bits.\n"); in rvu_ndc_fix_locked_cacheline()
581 ndc_af_const = rvu_read64(rvu, blkaddr, NDC_AF_CONST); in rvu_ndc_fix_locked_cacheline()
590 reg = rvu_read64(rvu, blkaddr, in rvu_ndc_fix_locked_cacheline()
593 rvu_write64(rvu, blkaddr, in rvu_ndc_fix_locked_cacheline()