Lines Matching refs:spx5_rmw
389 spx5_rmw(EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(1), in sparx5_init_switchcore()
394 spx5_rmw(EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(0), in sparx5_init_switchcore()
489 spx5_rmw(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(clk_div) | in sparx5_init_coreclock()
506 spx5_rmw(HSCH_SYS_CLK_PER_100PS_SET(clk_period / 100), in sparx5_init_coreclock()
511 spx5_rmw(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_SET(clk_period / 100), in sparx5_init_coreclock()
516 spx5_rmw(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_SET(clk_period / 100), in sparx5_init_coreclock()
521 spx5_rmw(LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_SET(clk_period / 100), in sparx5_init_coreclock()
527 spx5_rmw(GCB_SIO_CLOCK_SYS_CLK_PERIOD_SET(clk_period / 100), in sparx5_init_coreclock()
532 spx5_rmw(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_SET in sparx5_init_coreclock()
538 spx5_rmw(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_SET(pol_upd_int), in sparx5_init_coreclock()
580 spx5_rmw(GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL, in sparx5_board_init()
611 spx5_rmw(QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(1), in sparx5_start()
627 spx5_rmw(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_SET(1), in sparx5_start()