Lines Matching refs:portno
82 u32 portno = port->portno; in sparx5_get_dev2g5_status() local
87 value = spx5_rd(sparx5, DEV2G5_PCS1G_STICKY(portno)); in sparx5_get_dev2g5_status()
90 spx5_wr(value, sparx5, DEV2G5_PCS1G_STICKY(portno)); in sparx5_get_dev2g5_status()
93 value = spx5_rd(sparx5, DEV2G5_PCS1G_LINK_STATUS(portno)); in sparx5_get_dev2g5_status()
105 value = spx5_rd(sparx5, DEV2G5_PCS1G_ANEG_STATUS(portno)); in sparx5_get_dev2g5_status()
113 value = spx5_rd(sparx5, DEV2G5_PCS1G_ANEG_CFG(portno)); in sparx5_get_dev2g5_status()
126 u32 portno = port->portno; in sparx5_get_sfi_status() local
135 dev = sparx5_to_high_dev(portno); in sparx5_get_sfi_status()
136 tinst = sparx5_port_dev_index(portno); in sparx5_get_sfi_status()
216 if ((sparx5_port_is_2g5(port->portno) && in sparx5_port_verify_speed()
218 (sparx5_port_is_5g(port->portno) && in sparx5_port_verify_speed()
220 (sparx5_port_is_10g(port->portno) && in sparx5_port_verify_speed()
229 sparx5_port_is_2g5(port->portno)) in sparx5_port_verify_speed()
231 if (sparx5_port_is_2g5(port->portno)) in sparx5_port_verify_speed()
236 sparx5_port_is_2g5(port->portno)) in sparx5_port_verify_speed()
240 if (port->portno > 47) in sparx5_port_verify_speed()
272 static int sparx5_port_flush_poll(struct sparx5 *sparx5, u32 portno) in sparx5_port_flush_poll() argument
289 base = (resource == 0 ? 2048 : 0) + SPX5_PRIOS * portno; in sparx5_port_flush_poll()
307 portno, mem); in sparx5_port_flush_poll()
319 sparx5_port_dev_index(port->portno) : port->portno; in sparx5_port_disable()
321 sparx5_to_high_dev(port->portno) : TARGET_DEV2G5; in sparx5_port_disable()
355 QFWD_SWITCH_PORT_MODE(port->portno)); in sparx5_port_disable()
361 HSCH_PORT_MODE(port->portno)); in sparx5_port_disable()
367 QSYS_PAUSE_CFG(port->portno)); in sparx5_port_disable()
374 spx5_rmw(HSCH_FLUSH_CTRL_FLUSH_PORT_SET(port->portno) | in sparx5_port_disable()
389 HSCH_PORT_MODE(port->portno)); in sparx5_port_disable()
392 err = sparx5_port_flush_poll(sparx5, port->portno); in sparx5_port_disable()
422 spx5_rmw(HSCH_FLUSH_CTRL_FLUSH_PORT_SET(port->portno) | in sparx5_port_disable()
430 u32 pcs = sparx5_to_pcs_dev(port->portno); in sparx5_port_disable()
439 if (sparx5_port_is_25g(port->portno)) in sparx5_port_disable()
450 DEV2G5_PCS1G_CFG(port->portno)); in sparx5_port_disable()
458 u32 portno, u32 speed) in sparx5_port_fifo_sz() argument
507 tmp2 = 3000 + ((12000 + 2 * taxi_dist[portno] * 1000) in sparx5_port_fifo_sz()
520 u32 portno = port->portno; in sparx5_port_mux_set() local
528 inst = (portno - portno % 4) / 4; in sparx5_port_mux_set()
534 if ((portno / 4 % 2) == 0) { in sparx5_port_mux_set()
543 PORT_CONF_USGMII_CFG((portno / 8))); in sparx5_port_mux_set()
561 u32 dev = sparx5_to_high_dev(port->portno); in sparx5_port_max_tags_set()
562 u32 tinst = sparx5_port_dev_index(port->portno); in sparx5_port_max_tags_set()
576 DEV2G5_MAC_TAGS_CFG(port->portno)); in sparx5_port_max_tags_set()
578 if (sparx5_port_is_2g5(port->portno)) in sparx5_port_max_tags_set()
650 DSM_MAC_CFG(port->portno)); in sparx5_port_fc_setup()
656 DSM_RX_PAUSE_CFG(port->portno)); in sparx5_port_fc_setup()
662 QSYS_FWD_PRESSURE(port->portno)); in sparx5_port_fc_setup()
668 QSYS_PAUSE_CFG(port->portno)); in sparx5_port_fc_setup()
688 ((port->portno % 4) != 0)) { in sparx5_serdes_set()
753 DEV2G5_PCS1G_MODE_CFG(port->portno)); in sparx5_port_pcs_low_set()
758 DEV2G5_PCS1G_CFG(port->portno)); in sparx5_port_pcs_low_set()
769 DEV2G5_PCS1G_ANEG_CFG(port->portno)); in sparx5_port_pcs_low_set()
771 spx5_wr(0, sparx5, DEV2G5_PCS1G_ANEG_CFG(port->portno)); in sparx5_port_pcs_low_set()
782 DEV2G5_DEV_RST_CTRL(port->portno)); in sparx5_port_pcs_low_set()
792 u32 pix = sparx5_port_dev_index(port->portno); in sparx5_port_pcs_high_set()
793 u32 dev = sparx5_to_high_dev(port->portno); in sparx5_port_pcs_high_set()
794 u32 pcs = sparx5_to_pcs_dev(port->portno); in sparx5_port_pcs_high_set()
887 DEV2G5_MAC_MODE_CFG(port->portno)); in sparx5_port_config_low_set()
894 DEV2G5_MAC_IFG_CFG(port->portno)); in sparx5_port_config_low_set()
900 HSCH_PORT_MODE(port->portno)); in sparx5_port_config_low_set()
906 DEV2G5_MAC_ENA_CFG(port->portno)); in sparx5_port_config_low_set()
916 DEV2G5_DEV_RST_CTRL(port->portno)); in sparx5_port_config_low_set()
931 sparx5_dev_switch(sparx5, port->portno, high_speed_dev); in sparx5_port_pcs_set()
956 ASM_PORT_CFG(port->portno)); in sparx5_port_pcs_set()
962 DSM_BUF_CFG(port->portno)); in sparx5_port_pcs_set()
991 stop_wm = sparx5_port_fifo_sz(sparx5, port->portno, conf->speed); in sparx5_port_config()
995 DSM_DEV_TX_STOP_WM_CFG(port->portno)); in sparx5_port_config()
1004 QFWD_SWITCH_PORT_MODE(port->portno)); in sparx5_port_config()
1019 u32 devhigh = sparx5_to_high_dev(port->portno); in sparx5_port_init()
1020 u32 pix = sparx5_port_dev_index(port->portno); in sparx5_port_init()
1021 u32 pcs = sparx5_to_pcs_dev(port->portno); in sparx5_port_init()
1047 DEV2G5_MAC_MAXLEN_CFG(port->portno)); in sparx5_port_init()
1054 DEV2G5_PCS1G_SD_CFG(port->portno)); in sparx5_port_init()
1064 QSYS_PAUSE_CFG(port->portno)); in sparx5_port_init()
1069 QSYS_ATOP(port->portno)); in sparx5_port_init()
1072 spx5_wr(PAUSE_DISCARD, sparx5, ANA_CL_CAPTURE_BPDU_CFG(port->portno)); in sparx5_port_init()
1077 sparx5, ANA_CL_FILTER_CTRL(port->portno)); in sparx5_port_init()
1085 if (!sparx5_port_is_2g5(port->portno)) in sparx5_port_init()
1090 DSM_DEV_TX_STOP_WM_CFG(port->portno)); in sparx5_port_init()
1092 sparx5_dev_switch(sparx5, port->portno, false); in sparx5_port_init()
1099 DEV2G5_DEV_RST_CTRL(port->portno)); in sparx5_port_init()
1106 DEV2G5_MAC_IFG_CFG(port->portno)); in sparx5_port_init()
1108 if (sparx5_port_is_2g5(port->portno)) in sparx5_port_init()
1116 sparx5_dev_switch(sparx5, port->portno, true); in sparx5_port_init()
1131 if (sparx5_port_is_25g(port->portno)) { in sparx5_port_init()
1151 QFWD_SWITCH_PORT_MODE(port->portno)); in sparx5_port_enable()
1183 port->sparx5, REW_TAG_CTRL(port->portno)); in sparx5_port_qos_pcp_rewr_set()
1203 REW_PCP_MAP_DE1(port->portno, i)); in sparx5_port_qos_pcp_rewr_set()
1207 REW_DEI_MAP_DE1(port->portno, i)); in sparx5_port_qos_pcp_rewr_set()
1211 REW_PCP_MAP_DE0(port->portno, i)); in sparx5_port_qos_pcp_rewr_set()
1215 REW_DEI_MAP_DE0(port->portno, i)); in sparx5_port_qos_pcp_rewr_set()
1234 sparx5, ANA_CL_QOS_CFG(port->portno)); in sparx5_port_qos_pcp_set()
1244 ANA_CL_PCP_DEI_MAP_CFG(port->portno, i)); in sparx5_port_qos_pcp_set()
1255 ANA_CL_QOS_CFG(port->portno)); in sparx5_port_qos_dscp_rewr_mode_set()
1274 REW_DSCP_MAP(port->portno)); in sparx5_port_qos_dscp_rewr_set()
1304 ANA_CL_QOS_CFG(port->portno)); in sparx5_port_qos_dscp_set()
1337 sparx5, ANA_CL_QOS_CFG(port->portno)); in sparx5_port_qos_default_set()
1344 sparx5, ANA_CL_VLAN_CTRL(port->portno)); in sparx5_port_qos_default_set()