Lines Matching refs:bar0
1009 struct XENA_dev_config __iomem *bar0 = nic->bar0; in s2io_verify_pci_mode() local
1013 val64 = readq(&bar0->pci_mode); in s2io_verify_pci_mode()
1043 struct XENA_dev_config __iomem *bar0 = nic->bar0; in s2io_print_pci_mode() local
1049 val64 = readq(&bar0->pci_mode); in s2io_print_pci_mode()
1113 struct XENA_dev_config __iomem *bar0 = nic->bar0; in init_tti() local
1137 writeq(val64, &bar0->tti_data1_mem); in init_tti()
1162 writeq(val64, &bar0->tti_data2_mem); in init_tti()
1167 writeq(val64, &bar0->tti_command_mem); in init_tti()
1169 if (wait_for_cmd_complete(&bar0->tti_command_mem, in init_tti()
1189 struct XENA_dev_config __iomem *bar0 = nic->bar0; in init_nic() local
1212 writeq(val64, &bar0->sw_reset); in init_nic()
1214 val64 = readq(&bar0->sw_reset); in init_nic()
1219 writeq(val64, &bar0->sw_reset); in init_nic()
1221 val64 = readq(&bar0->sw_reset); in init_nic()
1228 val64 = readq(&bar0->adapter_status); in init_nic()
1238 add = &bar0->mac_cfg; in init_nic()
1239 val64 = readq(&bar0->mac_cfg); in init_nic()
1241 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); in init_nic()
1243 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); in init_nic()
1247 val64 = readq(&bar0->mac_int_mask); in init_nic()
1248 val64 = readq(&bar0->mc_int_mask); in init_nic()
1249 val64 = readq(&bar0->xgxs_int_mask); in init_nic()
1253 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len); in init_nic()
1258 &bar0->dtx_control, UF); in init_nic()
1266 &bar0->dtx_control, UF); in init_nic()
1267 val64 = readq(&bar0->dtx_control); in init_nic()
1274 writeq(val64, &bar0->tx_fifo_partition_0); in init_nic()
1275 writeq(val64, &bar0->tx_fifo_partition_1); in init_nic()
1276 writeq(val64, &bar0->tx_fifo_partition_2); in init_nic()
1277 writeq(val64, &bar0->tx_fifo_partition_3); in init_nic()
1292 writeq(val64, &bar0->tx_fifo_partition_0); in init_nic()
1297 writeq(val64, &bar0->tx_fifo_partition_1); in init_nic()
1302 writeq(val64, &bar0->tx_fifo_partition_2); in init_nic()
1307 writeq(val64, &bar0->tx_fifo_partition_3); in init_nic()
1322 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable); in init_nic()
1324 val64 = readq(&bar0->tx_fifo_partition_0); in init_nic()
1326 &bar0->tx_fifo_partition_0, (unsigned long long)val64); in init_nic()
1332 val64 = readq(&bar0->tx_pa_cfg); in init_nic()
1337 writeq(val64, &bar0->tx_pa_cfg); in init_nic()
1346 writeq(val64, &bar0->rx_queue_priority); in init_nic()
1395 writeq(val64, &bar0->rx_queue_cfg); in init_nic()
1404 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1405 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1406 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1407 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1408 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1412 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1413 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1414 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1415 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1417 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1421 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1423 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1425 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1427 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1429 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1433 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1434 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1435 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1436 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1438 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1442 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1444 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1446 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1448 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1450 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1454 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1456 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1458 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1460 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1462 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1466 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1468 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1470 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1472 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1474 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1478 writeq(val64, &bar0->tx_w_round_robin_0); in init_nic()
1479 writeq(val64, &bar0->tx_w_round_robin_1); in init_nic()
1480 writeq(val64, &bar0->tx_w_round_robin_2); in init_nic()
1481 writeq(val64, &bar0->tx_w_round_robin_3); in init_nic()
1483 writeq(val64, &bar0->tx_w_round_robin_4); in init_nic()
1488 val64 = readq(&bar0->tx_fifo_partition_0); in init_nic()
1490 writeq(val64, &bar0->tx_fifo_partition_0); in init_nic()
1499 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1500 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1501 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1502 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1503 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1506 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1510 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1511 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1512 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1513 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1515 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1518 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1522 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1524 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1526 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1528 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1530 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1533 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1537 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1538 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1539 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1540 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1542 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1545 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1549 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1551 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1553 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1555 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1557 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1560 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1564 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1566 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1568 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1570 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1572 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1575 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1579 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1581 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1583 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1585 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1587 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1590 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1594 writeq(val64, &bar0->rx_w_round_robin_0); in init_nic()
1595 writeq(val64, &bar0->rx_w_round_robin_1); in init_nic()
1596 writeq(val64, &bar0->rx_w_round_robin_2); in init_nic()
1597 writeq(val64, &bar0->rx_w_round_robin_3); in init_nic()
1599 writeq(val64, &bar0->rx_w_round_robin_4); in init_nic()
1602 writeq(val64, &bar0->rts_qos_steering); in init_nic()
1609 writeq(val64, &bar0->rts_frm_len_n[i]); in init_nic()
1614 writeq(val64, &bar0->rts_frm_len_n[i]); in init_nic()
1628 &bar0->rts_frm_len_n[i]); in init_nic()
1643 writeq(mac_control->stats_mem_phy, &bar0->stat_addr); in init_nic()
1647 writeq(val64, &bar0->stat_byte_cnt); in init_nic()
1656 writeq(val64, &bar0->mac_link_util); in init_nic()
1682 writeq(val64, &bar0->rti_data1_mem); in init_nic()
1692 writeq(val64, &bar0->rti_data2_mem); in init_nic()
1698 writeq(val64, &bar0->rti_command_mem); in init_nic()
1709 val64 = readq(&bar0->rti_command_mem); in init_nic()
1727 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3); in init_nic()
1728 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7); in init_nic()
1731 add = &bar0->mac_cfg; in init_nic()
1732 val64 = readq(&bar0->mac_cfg); in init_nic()
1734 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); in init_nic()
1736 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); in init_nic()
1738 val64 = readq(&bar0->mac_cfg); in init_nic()
1741 add = &bar0->mac_cfg; in init_nic()
1742 val64 = readq(&bar0->mac_cfg); in init_nic()
1745 writeq(val64, &bar0->mac_cfg); in init_nic()
1747 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); in init_nic()
1749 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); in init_nic()
1757 val64 = readq(&bar0->rmac_pause_cfg); in init_nic()
1760 writeq(val64, &bar0->rmac_pause_cfg); in init_nic()
1774 writeq(val64, &bar0->mc_pause_thresh_q0q3); in init_nic()
1782 writeq(val64, &bar0->mc_pause_thresh_q4q7); in init_nic()
1788 val64 = readq(&bar0->pic_control); in init_nic()
1790 writeq(val64, &bar0->pic_control); in init_nic()
1793 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout); in init_nic()
1794 writeq(0x0, &bar0->read_retry_delay); in init_nic()
1795 writeq(0x0, &bar0->write_retry_delay); in init_nic()
1805 writeq(val64, &bar0->misc_control); in init_nic()
1806 val64 = readq(&bar0->pic_control2); in init_nic()
1808 writeq(val64, &bar0->pic_control2); in init_nic()
1812 writeq(val64, &bar0->tmac_avg_ipg); in init_nic()
1852 struct XENA_dev_config __iomem *bar0 = nic->bar0; in en_dis_err_alarms() local
1856 writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask); in en_dis_err_alarms()
1863 TXDMA_SM_INT, flag, &bar0->txdma_int_mask); in en_dis_err_alarms()
1868 &bar0->pfc_err_mask); in en_dis_err_alarms()
1872 TDA_PCIX_ERR, flag, &bar0->tda_err_mask); in en_dis_err_alarms()
1880 flag, &bar0->pcc_err_mask); in en_dis_err_alarms()
1883 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask); in en_dis_err_alarms()
1888 flag, &bar0->lso_err_mask); in en_dis_err_alarms()
1891 flag, &bar0->tpa_err_mask); in en_dis_err_alarms()
1893 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask); in en_dis_err_alarms()
1899 &bar0->mac_int_mask); in en_dis_err_alarms()
1903 flag, &bar0->mac_tmac_err_mask); in en_dis_err_alarms()
1909 &bar0->xgxs_int_mask); in en_dis_err_alarms()
1912 flag, &bar0->xgxs_txgxs_err_mask); in en_dis_err_alarms()
1919 flag, &bar0->rxdma_int_mask); in en_dis_err_alarms()
1923 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask); in en_dis_err_alarms()
1927 &bar0->prc_pcix_err_mask); in en_dis_err_alarms()
1930 &bar0->rpa_err_mask); in en_dis_err_alarms()
1936 flag, &bar0->rda_err_mask); in en_dis_err_alarms()
1939 flag, &bar0->rti_err_mask); in en_dis_err_alarms()
1945 &bar0->mac_int_mask); in en_dis_err_alarms()
1952 flag, &bar0->mac_rmac_err_mask); in en_dis_err_alarms()
1958 &bar0->xgxs_int_mask); in en_dis_err_alarms()
1960 &bar0->xgxs_rxgxs_err_mask); in en_dis_err_alarms()
1966 flag, &bar0->mc_int_mask); in en_dis_err_alarms()
1969 &bar0->mc_err_mask); in en_dis_err_alarms()
1990 struct XENA_dev_config __iomem *bar0 = nic->bar0; in en_dis_able_nic_intrs() local
2010 &bar0->pic_int_mask); in en_dis_able_nic_intrs()
2012 &bar0->gpio_int_mask); in en_dis_able_nic_intrs()
2014 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask); in en_dis_able_nic_intrs()
2020 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask); in en_dis_able_nic_intrs()
2032 writeq(0x0, &bar0->tx_traffic_mask); in en_dis_able_nic_intrs()
2038 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask); in en_dis_able_nic_intrs()
2047 writeq(0x0, &bar0->rx_traffic_mask); in en_dis_able_nic_intrs()
2053 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask); in en_dis_able_nic_intrs()
2057 temp64 = readq(&bar0->general_int_mask); in en_dis_able_nic_intrs()
2062 writeq(temp64, &bar0->general_int_mask); in en_dis_able_nic_intrs()
2064 nic->general_int_mask = readq(&bar0->general_int_mask); in en_dis_able_nic_intrs()
2078 struct XENA_dev_config __iomem *bar0 = sp->bar0; in verify_pcc_quiescent() local
2079 u64 val64 = readq(&bar0->adapter_status); in verify_pcc_quiescent()
2120 struct XENA_dev_config __iomem *bar0 = sp->bar0; in verify_xena_quiescence() local
2121 u64 val64 = readq(&bar0->adapter_status); in verify_xena_quiescence()
2186 struct XENA_dev_config __iomem *bar0 = sp->bar0; in fix_mac_address() local
2190 writeq(fix_mac[i++], &bar0->gpio_control); in fix_mac_address()
2192 (void) readq(&bar0->gpio_control); in fix_mac_address()
2211 struct XENA_dev_config __iomem *bar0 = nic->bar0; in start_nic() local
2223 &bar0->prc_rxd0_n[i]); in start_nic()
2225 val64 = readq(&bar0->prc_ctrl_n[i]); in start_nic()
2234 writeq(val64, &bar0->prc_ctrl_n[i]); in start_nic()
2239 val64 = readq(&bar0->rx_pa_cfg); in start_nic()
2241 writeq(val64, &bar0->rx_pa_cfg); in start_nic()
2245 val64 = readq(&bar0->rx_pa_cfg); in start_nic()
2247 writeq(val64, &bar0->rx_pa_cfg); in start_nic()
2256 val64 = readq(&bar0->mc_rldram_mrs); in start_nic()
2258 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF); in start_nic()
2259 val64 = readq(&bar0->mc_rldram_mrs); in start_nic()
2264 val64 = readq(&bar0->adapter_control); in start_nic()
2266 writeq(val64, &bar0->adapter_control); in start_nic()
2272 val64 = readq(&bar0->adapter_status); in start_nic()
2289 val64 = readq(&bar0->adapter_control); in start_nic()
2291 writeq(val64, &bar0->adapter_control); in start_nic()
2304 val64 = readq(&bar0->gpio_control); in start_nic()
2306 writeq(val64, &bar0->gpio_control); in start_nic()
2308 writeq(val64, (void __iomem *)bar0 + 0x2700); in start_nic()
2414 struct XENA_dev_config __iomem *bar0 = nic->bar0; in stop_nic() local
2425 val64 = readq(&bar0->adapter_control); in stop_nic()
2427 writeq(val64, &bar0->adapter_control); in stop_nic()
2768 struct XENA_dev_config __iomem *bar0 = nic->bar0; in s2io_poll_msix() local
2780 addr = (u8 __iomem *)&bar0->xmsi_mask_reg; in s2io_poll_msix()
2794 struct XENA_dev_config __iomem *bar0 = nic->bar0; in s2io_poll_inta() local
2814 writeq(0, &bar0->rx_traffic_mask); in s2io_poll_inta()
2815 readl(&bar0->rx_traffic_mask); in s2io_poll_inta()
2834 struct XENA_dev_config __iomem *bar0 = nic->bar0; in s2io_netpoll() local
2845 writeq(val64, &bar0->rx_traffic_int); in s2io_netpoll()
2846 writeq(val64, &bar0->tx_traffic_int); in s2io_netpoll()
3090 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_mdio_write() local
3096 writeq(val64, &bar0->mdio_control); in s2io_mdio_write()
3098 writeq(val64, &bar0->mdio_control); in s2io_mdio_write()
3107 writeq(val64, &bar0->mdio_control); in s2io_mdio_write()
3109 writeq(val64, &bar0->mdio_control); in s2io_mdio_write()
3116 writeq(val64, &bar0->mdio_control); in s2io_mdio_write()
3118 writeq(val64, &bar0->mdio_control); in s2io_mdio_write()
3136 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_mdio_read() local
3142 writeq(val64, &bar0->mdio_control); in s2io_mdio_read()
3144 writeq(val64, &bar0->mdio_control); in s2io_mdio_read()
3152 writeq(val64, &bar0->mdio_control); in s2io_mdio_read()
3154 writeq(val64, &bar0->mdio_control); in s2io_mdio_read()
3158 rval64 = readq(&bar0->mdio_control); in s2io_mdio_read()
3402 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_reset() local
3419 writeq(val64, &bar0->sw_reset); in s2io_reset()
3459 writeq(s2BIT(62), &bar0->txpic_int_reg); in s2io_reset()
3494 val64 = readq(&bar0->gpio_control); in s2io_reset()
3496 writeq(val64, &bar0->gpio_control); in s2io_reset()
3498 writeq(val64, (void __iomem *)bar0 + 0x2700); in s2io_reset()
3506 val64 = readq(&bar0->pcc_err_reg); in s2io_reset()
3507 writeq(val64, &bar0->pcc_err_reg); in s2io_reset()
3526 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_set_swapper() local
3534 val64 = readq(&bar0->pif_rd_swapper_fb); in s2io_set_swapper()
3545 writeq(value[i], &bar0->swapper_ctrl); in s2io_set_swapper()
3546 val64 = readq(&bar0->pif_rd_swapper_fb); in s2io_set_swapper()
3559 valr = readq(&bar0->swapper_ctrl); in s2io_set_swapper()
3563 writeq(valt, &bar0->xmsi_address); in s2io_set_swapper()
3564 val64 = readq(&bar0->xmsi_address); in s2io_set_swapper()
3576 writeq((value[i] | valr), &bar0->swapper_ctrl); in s2io_set_swapper()
3577 writeq(valt, &bar0->xmsi_address); in s2io_set_swapper()
3578 val64 = readq(&bar0->xmsi_address); in s2io_set_swapper()
3590 val64 = readq(&bar0->swapper_ctrl); in s2io_set_swapper()
3611 writeq(val64, &bar0->swapper_ctrl); in s2io_set_swapper()
3635 writeq(val64, &bar0->swapper_ctrl); in s2io_set_swapper()
3637 val64 = readq(&bar0->swapper_ctrl); in s2io_set_swapper()
3643 val64 = readq(&bar0->pif_rd_swapper_fb); in s2io_set_swapper()
3657 struct XENA_dev_config __iomem *bar0 = nic->bar0; in wait_for_msix_trans() local
3662 val64 = readq(&bar0->xmsi_access); in wait_for_msix_trans()
3678 struct XENA_dev_config __iomem *bar0 = nic->bar0; in restore_xmsi_data() local
3687 writeq(nic->msix_info[i].addr, &bar0->xmsi_address); in restore_xmsi_data()
3688 writeq(nic->msix_info[i].data, &bar0->xmsi_data); in restore_xmsi_data()
3690 writeq(val64, &bar0->xmsi_access); in restore_xmsi_data()
3699 struct XENA_dev_config __iomem *bar0 = nic->bar0; in store_xmsi_data() local
3710 writeq(val64, &bar0->xmsi_access); in store_xmsi_data()
3716 addr = readq(&bar0->xmsi_address); in store_xmsi_data()
3717 data = readq(&bar0->xmsi_data); in store_xmsi_data()
3727 struct XENA_dev_config __iomem *bar0 = nic->bar0; in s2io_enable_msi_x() local
3771 rx_mat = readq(&bar0->rx_mat); in s2io_enable_msi_x()
3779 writeq(rx_mat, &bar0->rx_mat); in s2io_enable_msi_x()
3780 readq(&bar0->rx_mat); in s2io_enable_msi_x()
3824 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_test_msi() local
3839 saved64 = val64 = readq(&bar0->scheduled_int_ctrl); in s2io_test_msi()
3843 writeq(val64, &bar0->scheduled_int_ctrl); in s2io_test_msi()
3858 writeq(saved64, &bar0->scheduled_int_ctrl); in s2io_test_msi()
4208 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_msix_ring_handle() local
4217 addr = (u8 __iomem *)&bar0->xmsi_mask_reg; in s2io_msix_ring_handle()
4236 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_msix_fifo_handle() local
4243 reason = readq(&bar0->general_int_status); in s2io_msix_fifo_handle()
4249 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask); in s2io_msix_fifo_handle()
4255 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int); in s2io_msix_fifo_handle()
4260 writeq(sp->general_int_mask, &bar0->general_int_mask); in s2io_msix_fifo_handle()
4261 readl(&bar0->general_int_status); in s2io_msix_fifo_handle()
4270 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_txpic_intr_handle() local
4273 val64 = readq(&bar0->pic_int_status); in s2io_txpic_intr_handle()
4275 val64 = readq(&bar0->gpio_int_reg); in s2io_txpic_intr_handle()
4284 writeq(val64, &bar0->gpio_int_reg); in s2io_txpic_intr_handle()
4285 val64 = readq(&bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4288 writeq(val64, &bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4290 val64 = readq(&bar0->adapter_status); in s2io_txpic_intr_handle()
4292 val64 = readq(&bar0->adapter_control); in s2io_txpic_intr_handle()
4294 writeq(val64, &bar0->adapter_control); in s2io_txpic_intr_handle()
4296 writeq(val64, &bar0->adapter_control); in s2io_txpic_intr_handle()
4305 val64 = readq(&bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4308 writeq(val64, &bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4311 val64 = readq(&bar0->adapter_status); in s2io_txpic_intr_handle()
4314 val64 = readq(&bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4317 writeq(val64, &bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4320 val64 = readq(&bar0->adapter_control); in s2io_txpic_intr_handle()
4322 writeq(val64, &bar0->adapter_control); in s2io_txpic_intr_handle()
4325 val64 = readq(&bar0->gpio_int_mask); in s2io_txpic_intr_handle()
4364 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_handle_errors() local
4392 val64 = readq(&bar0->mac_rmac_err_reg); in s2io_handle_errors()
4393 writeq(val64, &bar0->mac_rmac_err_reg); in s2io_handle_errors()
4399 if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source, in s2io_handle_errors()
4404 if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg, in s2io_handle_errors()
4410 val64 = readq(&bar0->ring_bump_counter1); in s2io_handle_errors()
4417 val64 = readq(&bar0->ring_bump_counter2); in s2io_handle_errors()
4425 val64 = readq(&bar0->txdma_int_status); in s2io_handle_errors()
4431 &bar0->pfc_err_reg, in s2io_handle_errors()
4435 &bar0->pfc_err_reg, in s2io_handle_errors()
4444 &bar0->tda_err_reg, in s2io_handle_errors()
4448 &bar0->tda_err_reg, in s2io_handle_errors()
4458 &bar0->pcc_err_reg, in s2io_handle_errors()
4462 &bar0->pcc_err_reg, in s2io_handle_errors()
4469 &bar0->tti_err_reg, in s2io_handle_errors()
4473 &bar0->tti_err_reg, in s2io_handle_errors()
4481 &bar0->lso_err_reg, in s2io_handle_errors()
4485 &bar0->lso_err_reg, in s2io_handle_errors()
4492 &bar0->tpa_err_reg, in s2io_handle_errors()
4496 &bar0->tpa_err_reg, in s2io_handle_errors()
4503 &bar0->sm_err_reg, in s2io_handle_errors()
4508 val64 = readq(&bar0->mac_int_status); in s2io_handle_errors()
4511 &bar0->mac_tmac_err_reg, in s2io_handle_errors()
4517 &bar0->mac_tmac_err_reg, in s2io_handle_errors()
4521 val64 = readq(&bar0->xgxs_int_status); in s2io_handle_errors()
4524 &bar0->xgxs_txgxs_err_reg, in s2io_handle_errors()
4528 &bar0->xgxs_txgxs_err_reg, in s2io_handle_errors()
4532 val64 = readq(&bar0->rxdma_int_status); in s2io_handle_errors()
4538 &bar0->rc_err_reg, in s2io_handle_errors()
4543 RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg, in s2io_handle_errors()
4548 &bar0->prc_pcix_err_reg, in s2io_handle_errors()
4554 &bar0->prc_pcix_err_reg, in s2io_handle_errors()
4560 &bar0->rpa_err_reg, in s2io_handle_errors()
4564 &bar0->rpa_err_reg, in s2io_handle_errors()
4574 &bar0->rda_err_reg, in s2io_handle_errors()
4581 &bar0->rda_err_reg, in s2io_handle_errors()
4587 &bar0->rti_err_reg, in s2io_handle_errors()
4591 &bar0->rti_err_reg, in s2io_handle_errors()
4595 val64 = readq(&bar0->mac_int_status); in s2io_handle_errors()
4598 &bar0->mac_rmac_err_reg, in s2io_handle_errors()
4604 &bar0->mac_rmac_err_reg, in s2io_handle_errors()
4608 val64 = readq(&bar0->xgxs_int_status); in s2io_handle_errors()
4611 &bar0->xgxs_rxgxs_err_reg, in s2io_handle_errors()
4616 val64 = readq(&bar0->mc_int_status); in s2io_handle_errors()
4619 &bar0->mc_err_reg, in s2io_handle_errors()
4625 writeq(val64, &bar0->mc_err_reg); in s2io_handle_errors()
4666 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_isr() local
4689 reason = readq(&bar0->general_int_status); in s2io_isr()
4696 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask); in s2io_isr()
4701 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask); in s2io_isr()
4702 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int); in s2io_isr()
4703 readl(&bar0->rx_traffic_int); in s2io_isr()
4712 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int); in s2io_isr()
4727 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int); in s2io_isr()
4745 writeq(sp->general_int_mask, &bar0->general_int_mask); in s2io_isr()
4746 readl(&bar0->general_int_status); in s2io_isr()
4763 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_updt_stats() local
4771 writeq(val64, &bar0->stat_cfg); in s2io_updt_stats()
4774 val64 = readq(&bar0->stat_cfg); in s2io_updt_stats()
4891 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_set_multicast() local
4901 &bar0->rmac_addr_data0_mem); in s2io_set_multicast()
4903 &bar0->rmac_addr_data1_mem); in s2io_set_multicast()
4907 writeq(val64, &bar0->rmac_addr_cmd_mem); in s2io_set_multicast()
4909 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, in s2io_set_multicast()
4918 &bar0->rmac_addr_data0_mem); in s2io_set_multicast()
4920 &bar0->rmac_addr_data1_mem); in s2io_set_multicast()
4924 writeq(val64, &bar0->rmac_addr_cmd_mem); in s2io_set_multicast()
4926 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, in s2io_set_multicast()
4936 add = &bar0->mac_cfg; in s2io_set_multicast()
4937 val64 = readq(&bar0->mac_cfg); in s2io_set_multicast()
4940 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); in s2io_set_multicast()
4942 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); in s2io_set_multicast()
4946 val64 = readq(&bar0->rx_pa_cfg); in s2io_set_multicast()
4948 writeq(val64, &bar0->rx_pa_cfg); in s2io_set_multicast()
4952 val64 = readq(&bar0->mac_cfg); in s2io_set_multicast()
4958 add = &bar0->mac_cfg; in s2io_set_multicast()
4959 val64 = readq(&bar0->mac_cfg); in s2io_set_multicast()
4962 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); in s2io_set_multicast()
4964 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key); in s2io_set_multicast()
4968 val64 = readq(&bar0->rx_pa_cfg); in s2io_set_multicast()
4970 writeq(val64, &bar0->rx_pa_cfg); in s2io_set_multicast()
4974 val64 = readq(&bar0->mac_cfg); in s2io_set_multicast()
4996 &bar0->rmac_addr_data0_mem); in s2io_set_multicast()
4998 &bar0->rmac_addr_data1_mem); in s2io_set_multicast()
5003 writeq(val64, &bar0->rmac_addr_cmd_mem); in s2io_set_multicast()
5006 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, in s2io_set_multicast()
5026 &bar0->rmac_addr_data0_mem); in s2io_set_multicast()
5028 &bar0->rmac_addr_data1_mem); in s2io_set_multicast()
5033 writeq(val64, &bar0->rmac_addr_cmd_mem); in s2io_set_multicast()
5036 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, in s2io_set_multicast()
5129 struct XENA_dev_config __iomem *bar0 = sp->bar0; in do_s2io_add_mac() local
5132 &bar0->rmac_addr_data0_mem); in do_s2io_add_mac()
5136 writeq(val64, &bar0->rmac_addr_cmd_mem); in do_s2io_add_mac()
5139 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, in do_s2io_add_mac()
5175 struct XENA_dev_config __iomem *bar0 = sp->bar0; in do_s2io_read_unicast_mc() local
5180 writeq(val64, &bar0->rmac_addr_cmd_mem); in do_s2io_read_unicast_mc()
5183 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, in do_s2io_read_unicast_mc()
5189 tmp64 = readq(&bar0->rmac_addr_data0_mem); in do_s2io_read_unicast_mc()
5381 reg = readq(sp->bar0 + i); in s2io_ethtool_gregs()
5391 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_set_led() local
5397 val64 = readq(&bar0->gpio_control); in s2io_set_led()
5403 writeq(val64, &bar0->gpio_control); in s2io_set_led()
5405 val64 = readq(&bar0->adapter_control); in s2io_set_led()
5411 writeq(val64, &bar0->adapter_control); in s2io_set_led()
5432 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_ethtool_set_led() local
5436 u64 val64 = readq(&bar0->adapter_control); in s2io_ethtool_set_led()
5445 sp->adapt_ctrl_org = readq(&bar0->gpio_control); in s2io_ethtool_set_led()
5458 writeq(sp->adapt_ctrl_org, &bar0->gpio_control); in s2io_ethtool_set_led()
5508 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_ethtool_getpause_data() local
5510 val64 = readq(&bar0->rmac_pause_cfg); in s2io_ethtool_getpause_data()
5534 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_ethtool_setpause_data() local
5536 val64 = readq(&bar0->rmac_pause_cfg); in s2io_ethtool_setpause_data()
5545 writeq(val64, &bar0->rmac_pause_cfg); in s2io_ethtool_setpause_data()
5570 struct XENA_dev_config __iomem *bar0 = sp->bar0; in read_eeprom() local
5578 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF); in read_eeprom()
5581 val64 = readq(&bar0->i2c_control); in read_eeprom()
5596 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF); in read_eeprom()
5598 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF); in read_eeprom()
5600 val64 = readq(&bar0->spi_control); in read_eeprom()
5605 *data = readq(&bar0->spi_data); in read_eeprom()
5636 struct XENA_dev_config __iomem *bar0 = sp->bar0; in write_eeprom() local
5644 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF); in write_eeprom()
5647 val64 = readq(&bar0->i2c_control); in write_eeprom()
5660 writeq(SPI_DATA_WRITE(data, (cnt << 3)), &bar0->spi_data); in write_eeprom()
5665 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF); in write_eeprom()
5667 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF); in write_eeprom()
5669 val64 = readq(&bar0->spi_control); in write_eeprom()
5855 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_register_test() local
5859 val64 = readq(&bar0->pif_rd_swapper_fb); in s2io_register_test()
5865 val64 = readq(&bar0->rmac_pause_cfg); in s2io_register_test()
5871 val64 = readq(&bar0->rx_queue_cfg); in s2io_register_test()
5881 val64 = readq(&bar0->xgxs_efifo_cfg); in s2io_register_test()
5888 writeq(val64, &bar0->xmsi_data); in s2io_register_test()
5889 val64 = readq(&bar0->xmsi_data); in s2io_register_test()
5896 writeq(val64, &bar0->xmsi_data); in s2io_register_test()
5897 val64 = readq(&bar0->xmsi_data); in s2io_register_test()
6060 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_link_test() local
6063 val64 = readq(&bar0->adapter_status); in s2io_link_test()
6087 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_rldram_test() local
6091 val64 = readq(&bar0->adapter_control); in s2io_rldram_test()
6093 writeq(val64, &bar0->adapter_control); in s2io_rldram_test()
6095 val64 = readq(&bar0->mc_rldram_test_ctrl); in s2io_rldram_test()
6097 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF); in s2io_rldram_test()
6099 val64 = readq(&bar0->mc_rldram_mrs); in s2io_rldram_test()
6101 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF); in s2io_rldram_test()
6104 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF); in s2io_rldram_test()
6110 writeq(val64, &bar0->mc_rldram_test_d0); in s2io_rldram_test()
6115 writeq(val64, &bar0->mc_rldram_test_d1); in s2io_rldram_test()
6120 writeq(val64, &bar0->mc_rldram_test_d2); in s2io_rldram_test()
6123 writeq(val64, &bar0->mc_rldram_test_add); in s2io_rldram_test()
6128 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF); in s2io_rldram_test()
6131 val64 = readq(&bar0->mc_rldram_test_ctrl); in s2io_rldram_test()
6141 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF); in s2io_rldram_test()
6144 val64 = readq(&bar0->mc_rldram_test_ctrl); in s2io_rldram_test()
6153 val64 = readq(&bar0->mc_rldram_test_ctrl); in s2io_rldram_test()
6163 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF); in s2io_rldram_test()
6658 struct XENA_dev_config __iomem *bar0 = sp->bar0; in s2io_change_mtu() local
6661 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len); in s2io_change_mtu()
6678 struct XENA_dev_config __iomem *bar0 = nic->bar0; in s2io_set_link() local
6701 val64 = readq(&bar0->adapter_status); in s2io_set_link()
6703 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) { in s2io_set_link()
6705 val64 = readq(&bar0->adapter_control); in s2io_set_link()
6707 writeq(val64, &bar0->adapter_control); in s2io_set_link()
6710 val64 = readq(&bar0->gpio_control); in s2io_set_link()
6712 writeq(val64, &bar0->gpio_control); in s2io_set_link()
6713 val64 = readq(&bar0->gpio_control); in s2io_set_link()
6716 writeq(val64, &bar0->adapter_control); in s2io_set_link()
6726 val64 = readq(&bar0->adapter_control); in s2io_set_link()
6728 writeq(val64, &bar0->adapter_control); in s2io_set_link()
6733 val64 = readq(&bar0->gpio_control); in s2io_set_link()
6735 writeq(val64, &bar0->gpio_control); in s2io_set_link()
6736 val64 = readq(&bar0->gpio_control); in s2io_set_link()
6739 val64 = readq(&bar0->adapter_control); in s2io_set_link()
6741 writeq(val64, &bar0->adapter_control); in s2io_set_link()
7020 struct XENA_dev_config __iomem *bar0 = sp->bar0; in do_s2io_card_down() local
7065 val64 = readq(&bar0->adapter_status); in do_s2io_card_down()
7614 struct XENA_dev_config __iomem *bar0 = nic->bar0; in rts_ds_steer() local
7621 writeq(val64, &bar0->rts_ds_mem_data); in rts_ds_steer()
7627 writeq(val64, &bar0->rts_ds_mem_ctrl); in rts_ds_steer()
7629 return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl, in rts_ds_steer()
7673 struct XENA_dev_config __iomem *bar0 = NULL; in s2io_init_nic() local
7842 sp->bar0 = pci_ioremap_bar(pdev, 0); in s2io_init_nic()
7843 if (!sp->bar0) { in s2io_init_nic()
7938 bar0 = sp->bar0; in s2io_init_nic()
7941 writeq(val64, &bar0->rmac_addr_cmd_mem); in s2io_init_nic()
7942 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem, in s2io_init_nic()
7945 tmp64 = readq(&bar0->rmac_addr_data0_mem); in s2io_init_nic()
8007 val64 = readq(&bar0->gpio_control); in s2io_init_nic()
8009 writeq(val64, &bar0->gpio_control); in s2io_init_nic()
8011 writeq(val64, (void __iomem *)bar0 + 0x2700); in s2io_init_nic()
8012 val64 = readq(&bar0->gpio_control); in s2io_init_nic()
8124 iounmap(sp->bar0); in s2io_init_nic()
8162 iounmap(sp->bar0); in s2io_rem_nic()