Lines Matching refs:cr
288 u32 cr; in nixge_hw_dma_bd_init() local
345 cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET); in nixge_hw_dma_bd_init()
347 cr = ((cr & ~XAXIDMA_COALESCE_MASK) | in nixge_hw_dma_bd_init()
350 cr = ((cr & ~XAXIDMA_DELAY_MASK) | in nixge_hw_dma_bd_init()
353 cr |= XAXIDMA_IRQ_ALL_MASK; in nixge_hw_dma_bd_init()
355 nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, cr); in nixge_hw_dma_bd_init()
358 cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET); in nixge_hw_dma_bd_init()
360 cr = (((cr & ~XAXIDMA_COALESCE_MASK)) | in nixge_hw_dma_bd_init()
363 cr = (((cr & ~XAXIDMA_DELAY_MASK)) | in nixge_hw_dma_bd_init()
366 cr |= XAXIDMA_IRQ_ALL_MASK; in nixge_hw_dma_bd_init()
368 nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET, cr); in nixge_hw_dma_bd_init()
374 cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET); in nixge_hw_dma_bd_init()
376 cr | XAXIDMA_CR_RUNSTOP_MASK); in nixge_hw_dma_bd_init()
385 cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET); in nixge_hw_dma_bd_init()
387 cr | XAXIDMA_CR_RUNSTOP_MASK); in nixge_hw_dma_bd_init()
675 u32 status, cr; in nixge_poll() local
690 cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET); in nixge_poll()
691 cr |= (XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK); in nixge_poll()
692 nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, cr); in nixge_poll()
705 u32 cr; in nixge_tx_irq() local
724 cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET); in nixge_tx_irq()
726 cr &= (~XAXIDMA_IRQ_ALL_MASK); in nixge_tx_irq()
728 nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET, cr); in nixge_tx_irq()
730 cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET); in nixge_tx_irq()
732 cr &= (~XAXIDMA_IRQ_ALL_MASK); in nixge_tx_irq()
734 nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, cr); in nixge_tx_irq()
749 u32 cr; in nixge_rx_irq() local
755 cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET); in nixge_rx_irq()
756 cr &= ~(XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK); in nixge_rx_irq()
757 nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, cr); in nixge_rx_irq()
773 cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET); in nixge_rx_irq()
775 cr &= (~XAXIDMA_IRQ_ALL_MASK); in nixge_rx_irq()
777 nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET, cr); in nixge_rx_irq()
779 cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET); in nixge_rx_irq()
781 cr &= (~XAXIDMA_IRQ_ALL_MASK); in nixge_rx_irq()
783 nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, cr); in nixge_rx_irq()
797 u32 cr, i; in nixge_dma_err_handler() local
823 cr = nixge_dma_read_reg(lp, XAXIDMA_RX_CR_OFFSET); in nixge_dma_err_handler()
825 cr = ((cr & ~XAXIDMA_COALESCE_MASK) | in nixge_dma_err_handler()
828 cr = ((cr & ~XAXIDMA_DELAY_MASK) | in nixge_dma_err_handler()
831 cr |= XAXIDMA_IRQ_ALL_MASK; in nixge_dma_err_handler()
833 nixge_dma_write_reg(lp, XAXIDMA_RX_CR_OFFSET, cr); in nixge_dma_err_handler()
836 cr = nixge_dma_read_reg(lp, XAXIDMA_TX_CR_OFFSET); in nixge_dma_err_handler()
838 cr = (((cr & ~XAXIDMA_COALESCE_MASK)) | in nixge_dma_err_handler()
841 cr = (((cr & ~XAXIDMA_DELAY_MASK)) | in nixge_dma_err_handler()
844 cr |= XAXIDMA_IRQ_ALL_MASK; in nixge_dma_err_handler()
846 nixge_dma_write_reg(lp, XAXIDMA_TX_CR_OFFSET, cr); in nixge_dma_err_handler()
852 cr = nixge_dma_read_reg(lp, XAXIDMA_RX_CR_OFFSET); in nixge_dma_err_handler()
854 cr | XAXIDMA_CR_RUNSTOP_MASK); in nixge_dma_err_handler()
863 cr = nixge_dma_read_reg(lp, XAXIDMA_TX_CR_OFFSET); in nixge_dma_err_handler()
865 cr | XAXIDMA_CR_RUNSTOP_MASK); in nixge_dma_err_handler()
915 u32 cr; in nixge_stop() local
925 cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET); in nixge_stop()
927 cr & (~XAXIDMA_CR_RUNSTOP_MASK)); in nixge_stop()
928 cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET); in nixge_stop()
930 cr & (~XAXIDMA_CR_RUNSTOP_MASK)); in nixge_stop()