Lines Matching refs:phyaddr
768 int phyaddr; member
1185 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) in phy_reset()
1194 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in phy_reset()
1219 if (mii_rw(dev, np->phyaddr, ri[i].reg, ri[i].init)) in init_realtek_8211b()
1241 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ); in init_realtek_8211c()
1243 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg)) in init_realtek_8211c()
1245 if (mii_rw(dev, np->phyaddr, in init_realtek_8211c()
1248 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ); in init_realtek_8211c()
1251 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg)) in init_realtek_8211c()
1254 if (mii_rw(dev, np->phyaddr, in init_realtek_8211c()
1266 phy_reserved = mii_rw(dev, np->phyaddr, in init_realtek_8201()
1269 if (mii_rw(dev, np->phyaddr, in init_realtek_8201()
1282 if (mii_rw(dev, np->phyaddr, in init_realtek_8201_cross()
1285 phy_reserved = mii_rw(dev, np->phyaddr, in init_realtek_8201_cross()
1289 if (mii_rw(dev, np->phyaddr, in init_realtek_8201_cross()
1292 if (mii_rw(dev, np->phyaddr, in init_realtek_8201_cross()
1306 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ); in init_cicada()
1309 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) in init_cicada()
1311 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); in init_cicada()
1313 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) in init_cicada()
1316 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ); in init_cicada()
1318 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) in init_cicada()
1328 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1331 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1334 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1336 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) in init_vitesse()
1338 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1342 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) in init_vitesse()
1344 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1347 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1350 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1354 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) in init_vitesse()
1356 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1358 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) in init_vitesse()
1360 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1363 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1366 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1368 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved)) in init_vitesse()
1370 phy_reserved = mii_rw(dev, np->phyaddr, in init_vitesse()
1374 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved)) in init_vitesse()
1376 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1379 if (mii_rw(dev, np->phyaddr, in init_vitesse()
1395 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ); in phy_init()
1397 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) { in phy_init()
1428 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in phy_init()
1432 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) { in phy_init()
1442 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in phy_init()
1445 mii_control_1000 = mii_rw(dev, np->phyaddr, in phy_init()
1453 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) { in phy_init()
1461 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in phy_init()
1469 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) { in phy_init()
1518 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg); in phy_init()
1521 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in phy_init()
1525 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) in phy_init()
3314 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_force_linkspeed()
3398 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_update_linkspeed()
3411 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_update_linkspeed()
3412 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_update_linkspeed()
3447 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in nv_update_linkspeed()
3448 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ); in nv_update_linkspeed()
3452 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); in nv_update_linkspeed()
3453 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ); in nv_update_linkspeed()
3520 phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */ in nv_update_linkspeed()
4378 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in nv_get_link_ksettings()
4388 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); in nv_get_link_ksettings()
4400 cmd->base.phy_address = np->phyaddr; in nv_get_link_ksettings()
4424 if (cmd->base.phy_address != np->phyaddr) { in nv_set_link_ksettings()
4483 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in nv_set_link_ksettings()
4497 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); in nv_set_link_ksettings()
4500 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); in nv_set_link_ksettings()
4504 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv); in nv_set_link_ksettings()
4509 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_set_link_ksettings()
4520 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); in nv_set_link_ksettings()
4527 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in nv_set_link_ksettings()
4546 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); in nv_set_link_ksettings()
4550 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ); in nv_set_link_ksettings()
4552 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv); in nv_set_link_ksettings()
4555 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_set_link_ksettings()
4568 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); in nv_set_link_ksettings()
4629 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_nway_reset()
4639 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); in nv_nway_reset()
4841 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ); in nv_set_pauseparam()
4847 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv); in nv_set_pauseparam()
4851 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_set_pauseparam()
4853 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr); in nv_set_pauseparam()
4882 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_set_loopback()
4892 err = mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol); in nv_set_loopback()
5036 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_link_test()
5037 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_link_test()
5466 mii_rw(dev, np->phyaddr, MII_BMCR, in nv_open()
5467 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN); in nv_open()
5552 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING, in nv_open()
5665 mii_rw(dev, np->phyaddr, MII_BMCR, in nv_close()
5666 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN); in nv_close()
6050 int phyaddr = i & 0x1F; in nv_probe() local
6053 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ); in nv_probe()
6058 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ); in nv_probe()
6066 np->phyaddr = phyaddr; in nv_probe()
6074 np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK; in nv_probe()
6088 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ); in nv_probe()
6118 dev->name, np->phy_oui, np->phyaddr, dev->dev_addr); in nv_probe()
6167 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3); in nv_restore_phy()
6168 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ); in nv_restore_phy()
6171 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved); in nv_restore_phy()
6172 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1); in nv_restore_phy()
6175 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ); in nv_restore_phy()
6177 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control); in nv_restore_phy()