Lines Matching refs:ioaddr
193 static int atp_probe1(long ioaddr);
195 static unsigned short eeprom_op(long ioaddr, unsigned int cmd);
198 static void write_packet(long ioaddr, int length, unsigned char *packet, int pad, int mode);
199 static void trigger_send(long ioaddr, int length);
204 static void read_block(long ioaddr, int length, unsigned char *buffer, int data_mode);
232 long ioaddr = *port; in atp_init() local
233 outb(0x57, ioaddr + PAR_DATA); in atp_init()
234 if (inb(ioaddr + PAR_DATA) != 0x57) in atp_init()
236 if (atp_probe1(ioaddr) == 0) in atp_init()
253 static int __init atp_probe1(long ioaddr) in atp_probe1() argument
260 outb(0xff, ioaddr + PAR_DATA); in atp_probe1()
263 saved_ctrl_reg = inb(ioaddr + PAR_CONTROL); in atp_probe1()
267 outb(0x04, ioaddr + PAR_CONTROL); in atp_probe1()
272 outb(mux_8012[i], ioaddr + PAR_DATA); in atp_probe1()
273 write_reg(ioaddr, MODSEL, 0x00); in atp_probe1()
276 printk(" %2.2x", read_nibble(ioaddr, i)); in atp_probe1()
282 outb(mux_8012[i], ioaddr + PAR_DATA); in atp_probe1()
283 write_reg_high(ioaddr, CMR1, CMR1h_RESET); in atp_probe1()
285 status = read_nibble(ioaddr, CMR1); in atp_probe1()
290 printk(" %2.2x", read_nibble(ioaddr, i)); in atp_probe1()
296 outb(saved_ctrl_reg, ioaddr + PAR_CONTROL); in atp_probe1()
299 status = read_nibble(ioaddr, CMR2_h); in atp_probe1()
301 outb(saved_ctrl_reg, ioaddr + PAR_CONTROL); in atp_probe1()
310 write_reg_byte(ioaddr, CMR2, 0x01); /* No accept mode, IRQ out. */ in atp_probe1()
311 write_reg_high(ioaddr, CMR1, CMR1h_RxENABLE | CMR1h_TxENABLE); /* Enable Tx and Rx. */ in atp_probe1()
316 else if (ioaddr == 0x378) in atp_probe1()
320 write_reg_high(ioaddr, CMR1, CMR1h_TxRxOFF); /* Disable Tx and Rx units. */ in atp_probe1()
321 write_reg(ioaddr, CMR2, CMR2_NULL); in atp_probe1()
323 dev->base_addr = ioaddr; in atp_probe1()
338 write_reg_high(ioaddr, CMR1, CMR1h_RESET | CMR1h_MUX); in atp_probe1()
370 long ioaddr = dev->base_addr; in get_node_ID() local
375 write_reg(ioaddr, CMR2, CMR2_EEPROM); /* Point to the EEPROM control registers. */ in get_node_ID()
379 if (eeprom_op(ioaddr, EE_READ(0)) == 0xffff) in get_node_ID()
384 cpu_to_be16(eeprom_op(ioaddr, EE_READ(sa_offset + i))); in get_node_ID()
387 write_reg(ioaddr, CMR2, CMR2_NULL); in get_node_ID()
402 static unsigned short __init eeprom_op(long ioaddr, u32 cmd) in eeprom_op() argument
409 write_reg_high(ioaddr, PROM_CMD, outval | EE_CLK_LOW); in eeprom_op()
410 write_reg_high(ioaddr, PROM_CMD, outval | EE_CLK_HIGH); in eeprom_op()
412 if (read_nibble(ioaddr, PROM_DATA) & EE_DATA_READ) in eeprom_op()
415 write_reg_high(ioaddr, PROM_CMD, EE_CLK_LOW & ~EE_CS); in eeprom_op()
458 long ioaddr = dev->base_addr; in hardware_init() local
463 outb(mux_8012[i], ioaddr + PAR_DATA); in hardware_init()
464 write_reg_high(ioaddr, CMR1, CMR1h_RESET); in hardware_init()
467 write_reg_byte(ioaddr, PAR0 + i, dev->dev_addr[i]); in hardware_init()
469 write_reg_high(ioaddr, CMR2, lp->addr_mode); in hardware_init()
473 (read_nibble(ioaddr, CMR2_h) >> 3) & 0x0f); in hardware_init()
476 write_reg(ioaddr, CMR2, CMR2_IRQOUT); in hardware_init()
477 write_reg_high(ioaddr, CMR1, CMR1h_RxENABLE | CMR1h_TxENABLE); in hardware_init()
480 outb(Ctrl_SelData + Ctrl_IRQEN, ioaddr + PAR_CONTROL); in hardware_init()
483 write_reg(ioaddr, IMR, ISR_RxOK | ISR_TxErr | ISR_TxOK); in hardware_init()
484 write_reg_high(ioaddr, IMR, ISRh_RxErr); in hardware_init()
491 static void trigger_send(long ioaddr, int length) in trigger_send() argument
493 write_reg_byte(ioaddr, TxCNT0, length & 0xff); in trigger_send()
494 write_reg(ioaddr, TxCNT1, length >> 8); in trigger_send()
495 write_reg(ioaddr, CMR1, CMR1_Xmit); in trigger_send()
498 static void write_packet(long ioaddr, int length, unsigned char *packet, int pad_len, int data_mode) in write_packet() argument
506 outb(EOC+MAR, ioaddr + PAR_DATA); in write_packet()
509 outb(WrAddr+MAR, ioaddr + PAR_DATA); in write_packet()
511 write_byte_mode0(ioaddr, *packet++); in write_packet()
514 write_byte_mode0(ioaddr, 0); in write_packet()
520 outb(Ctrl_LNibWrite + Ctrl_IRQEN, ioaddr + PAR_CONTROL); in write_packet()
521 outb(WrAddr+MAR, ioaddr + PAR_DATA); in write_packet()
523 outb((outbyte & 0x0f)|0x40, ioaddr + PAR_DATA); in write_packet()
524 outb(outbyte & 0x0f, ioaddr + PAR_DATA); in write_packet()
526 outb(outbyte & 0x0f, ioaddr + PAR_DATA); in write_packet()
527 outb(Ctrl_HNibWrite + Ctrl_IRQEN, ioaddr + PAR_CONTROL); in write_packet()
529 write_byte_mode1(ioaddr, *packet++); in write_packet()
531 write_byte_mode1(ioaddr, 0); in write_packet()
534 outb(0xff, ioaddr + PAR_DATA); in write_packet()
535 outb(Ctrl_HNibWrite | Ctrl_SelData | Ctrl_IRQEN, ioaddr + PAR_CONTROL); in write_packet()
540 long ioaddr = dev->base_addr; in tx_timeout() local
543 inb(ioaddr + PAR_CONTROL) & 0x10 ? "network cable problem" in tx_timeout()
557 long ioaddr = dev->base_addr; in atp_send_packet() local
569 write_reg(ioaddr, IMR, 0); in atp_send_packet()
570 write_reg_high(ioaddr, IMR, 0); in atp_send_packet()
573 write_packet(ioaddr, length, skb->data, length-skb->len, dev->if_port); in atp_send_packet()
577 trigger_send(ioaddr, length); in atp_send_packet()
584 write_reg(ioaddr, IMR, ISR_RxOK | ISR_TxErr | ISR_TxOK); in atp_send_packet()
585 write_reg_high(ioaddr, IMR, ISRh_RxErr); in atp_send_packet()
598 long ioaddr; in atp_interrupt() local
603 ioaddr = dev->base_addr; in atp_interrupt()
609 outb(Ctrl_SelData, ioaddr + PAR_CONTROL); in atp_interrupt()
612 write_reg(ioaddr, CMR2, CMR2_NULL); in atp_interrupt()
613 write_reg(ioaddr, IMR, 0); in atp_interrupt()
618 int status = read_nibble(ioaddr, ISR); in atp_interrupt()
624 write_reg(ioaddr, ISR, ISR_RxOK); /* Clear the Rx interrupt. */ in atp_interrupt()
626 int read_status = read_nibble(ioaddr, CMR1); in atp_interrupt()
634 write_reg_high(ioaddr, CMR2, CMR2h_OFF); in atp_interrupt()
637 write_reg_high(ioaddr, ISR, ISRh_RxErr); in atp_interrupt()
638 write_reg_high(ioaddr, CMR2, lp->addr_mode); in atp_interrupt()
651 write_reg(ioaddr, ISR, ISR_TxErr + ISR_TxOK); in atp_interrupt()
661 write_reg(ioaddr, CMR1, CMR1_ReXmit + CMR1_Xmit); in atp_interrupt()
667 trigger_send(ioaddr, lp->saved_tx_size); in atp_interrupt()
681 (read_nibble(ioaddr, CMR1) >> 3) & 15); in atp_interrupt()
695 write_reg_byte(ioaddr, PAR0 + i, dev->dev_addr[i]); in atp_interrupt()
702 write_reg(ioaddr, CMR2, CMR2_IRQOUT); in atp_interrupt()
704 outb(Ctrl_SelData + Ctrl_IRQEN, ioaddr + PAR_CONTROL); in atp_interrupt()
706 write_reg(ioaddr, IMR, ISR_RxOK | ISR_TxErr | ISR_TxOK); in atp_interrupt()
707 write_reg_high(ioaddr, IMR, ISRh_RxErr); /* Hmmm, really needed? */ in atp_interrupt()
722 long ioaddr = dev->base_addr; in atp_timed_checker() local
730 write_reg_byte(ioaddr, PAR0 + i, dev->dev_addr[i]); in atp_timed_checker()
734 if (read_cmd_byte(ioaddr, PAR0 + i) != atp_timed_dev->dev_addr[i]) in atp_timed_checker()
737 write_reg_byte(ioaddr, PAR0 + i, atp_timed_dev->dev_addr[i]); in atp_timed_checker()
759 long ioaddr = dev->base_addr; in net_rx() local
763 outb(EOC+MAR, ioaddr + PAR_DATA); in net_rx()
764 read_block(ioaddr, 8, (unsigned char*)&rx_head, dev->if_port); in net_rx()
777 write_reg_high(ioaddr, CMR1, CMR1h_TxENABLE); in net_rx()
778 write_reg_high(ioaddr, CMR1, CMR1h_RxENABLE | CMR1h_TxENABLE); in net_rx()
794 read_block(ioaddr, pkt_len, skb_put(skb,pkt_len), dev->if_port); in net_rx()
801 write_reg(ioaddr, CMR1, CMR1_NextPkt); in net_rx()
805 static void read_block(long ioaddr, int length, unsigned char *p, int data_mode) in read_block() argument
808 outb(Ctrl_LNibRead, ioaddr + PAR_CONTROL); in read_block()
810 ioaddr + PAR_DATA); in read_block()
812 do { *p++ = read_byte_mode0(ioaddr); } while (--length > 0); in read_block()
814 do { *p++ = read_byte_mode2(ioaddr); } while (--length > 0); in read_block()
817 do { *p++ = read_byte_mode4(ioaddr); } while (--length > 0); in read_block()
819 do { *p++ = read_byte_mode6(ioaddr); } while (--length > 0); in read_block()
822 outb(EOC+HNib+MAR, ioaddr + PAR_DATA); in read_block()
823 outb(Ctrl_SelData, ioaddr + PAR_CONTROL); in read_block()
831 long ioaddr = dev->base_addr; in net_close() local
839 write_reg_high(ioaddr, CMR2, CMR2h_OFF); in net_close()
842 outb(0x00, ioaddr + PAR_CONTROL); in net_close()
846 write_reg_high(ioaddr, CMR1, CMR1h_RESET | CMR1h_MUX); in net_close()
857 long ioaddr = dev->base_addr; in set_rx_mode() local
863 write_reg_high(ioaddr, CMR2, lp->addr_mode); in set_rx_mode()