Lines Matching refs:ioaddr
21 static int sxgbe_dma_init(void __iomem *ioaddr, int fix_burst, int burst_map) in sxgbe_dma_init() argument
25 reg_val = readl(ioaddr + SXGBE_DMA_SYSBUS_MODE_REG); in sxgbe_dma_init()
38 writel(reg_val, ioaddr + SXGBE_DMA_SYSBUS_MODE_REG); in sxgbe_dma_init()
43 static void sxgbe_dma_channel_init(void __iomem *ioaddr, int cha_num, in sxgbe_dma_channel_init() argument
50 reg_val = readl(ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num)); in sxgbe_dma_channel_init()
54 writel(reg_val, ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num)); in sxgbe_dma_channel_init()
56 reg_val = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num)); in sxgbe_dma_channel_init()
58 writel(reg_val, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num)); in sxgbe_dma_channel_init()
60 reg_val = readl(ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cha_num)); in sxgbe_dma_channel_init()
62 writel(reg_val, ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cha_num)); in sxgbe_dma_channel_init()
67 ioaddr + SXGBE_DMA_CHA_TXDESC_HADD_REG(cha_num)); in sxgbe_dma_channel_init()
69 ioaddr + SXGBE_DMA_CHA_TXDESC_LADD_REG(cha_num)); in sxgbe_dma_channel_init()
72 ioaddr + SXGBE_DMA_CHA_RXDESC_HADD_REG(cha_num)); in sxgbe_dma_channel_init()
74 ioaddr + SXGBE_DMA_CHA_RXDESC_LADD_REG(cha_num)); in sxgbe_dma_channel_init()
82 ioaddr + SXGBE_DMA_CHA_TXDESC_TAILPTR_REG(cha_num)); in sxgbe_dma_channel_init()
86 ioaddr + SXGBE_DMA_CHA_RXDESC_LADD_REG(cha_num)); in sxgbe_dma_channel_init()
88 writel(t_rsize - 1, ioaddr + SXGBE_DMA_CHA_TXDESC_RINGLEN_REG(cha_num)); in sxgbe_dma_channel_init()
89 writel(r_rsize - 1, ioaddr + SXGBE_DMA_CHA_RXDESC_RINGLEN_REG(cha_num)); in sxgbe_dma_channel_init()
93 ioaddr + SXGBE_DMA_CHA_INT_ENABLE_REG(cha_num)); in sxgbe_dma_channel_init()
96 static void sxgbe_enable_dma_transmission(void __iomem *ioaddr, int cha_num) in sxgbe_enable_dma_transmission() argument
100 tx_config = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num)); in sxgbe_enable_dma_transmission()
102 writel(tx_config, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num)); in sxgbe_enable_dma_transmission()
105 static void sxgbe_enable_dma_irq(void __iomem *ioaddr, int dma_cnum) in sxgbe_enable_dma_irq() argument
109 ioaddr + SXGBE_DMA_CHA_INT_ENABLE_REG(dma_cnum)); in sxgbe_enable_dma_irq()
112 static void sxgbe_disable_dma_irq(void __iomem *ioaddr, int dma_cnum) in sxgbe_disable_dma_irq() argument
115 writel(0, ioaddr + SXGBE_DMA_CHA_INT_ENABLE_REG(dma_cnum)); in sxgbe_disable_dma_irq()
118 static void sxgbe_dma_start_tx(void __iomem *ioaddr, int tchannels) in sxgbe_dma_start_tx() argument
124 tx_ctl_reg = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cnum)); in sxgbe_dma_start_tx()
127 ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cnum)); in sxgbe_dma_start_tx()
131 static void sxgbe_dma_start_tx_queue(void __iomem *ioaddr, int dma_cnum) in sxgbe_dma_start_tx_queue() argument
135 tx_ctl_reg = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(dma_cnum)); in sxgbe_dma_start_tx_queue()
137 writel(tx_ctl_reg, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(dma_cnum)); in sxgbe_dma_start_tx_queue()
140 static void sxgbe_dma_stop_tx_queue(void __iomem *ioaddr, int dma_cnum) in sxgbe_dma_stop_tx_queue() argument
144 tx_ctl_reg = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(dma_cnum)); in sxgbe_dma_stop_tx_queue()
146 writel(tx_ctl_reg, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(dma_cnum)); in sxgbe_dma_stop_tx_queue()
149 static void sxgbe_dma_stop_tx(void __iomem *ioaddr, int tchannels) in sxgbe_dma_stop_tx() argument
155 tx_ctl_reg = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cnum)); in sxgbe_dma_stop_tx()
157 writel(tx_ctl_reg, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cnum)); in sxgbe_dma_stop_tx()
161 static void sxgbe_dma_start_rx(void __iomem *ioaddr, int rchannels) in sxgbe_dma_start_rx() argument
167 rx_ctl_reg = readl(ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cnum)); in sxgbe_dma_start_rx()
170 ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cnum)); in sxgbe_dma_start_rx()
174 static void sxgbe_dma_stop_rx(void __iomem *ioaddr, int rchannels) in sxgbe_dma_stop_rx() argument
180 rx_ctl_reg = readl(ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cnum)); in sxgbe_dma_stop_rx()
182 writel(rx_ctl_reg, ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cnum)); in sxgbe_dma_stop_rx()
186 static int sxgbe_tx_dma_int_status(void __iomem *ioaddr, int channel_no, in sxgbe_tx_dma_int_status() argument
189 u32 int_status = readl(ioaddr + SXGBE_DMA_CHA_STATUS_REG(channel_no)); in sxgbe_tx_dma_int_status()
253 writel(clear_val, ioaddr + SXGBE_DMA_CHA_STATUS_REG(channel_no)); in sxgbe_tx_dma_int_status()
258 static int sxgbe_rx_dma_int_status(void __iomem *ioaddr, int channel_no, in sxgbe_rx_dma_int_status() argument
261 u32 int_status = readl(ioaddr + SXGBE_DMA_CHA_STATUS_REG(channel_no)); in sxgbe_rx_dma_int_status()
319 writel(clear_val, ioaddr + SXGBE_DMA_CHA_STATUS_REG(channel_no)); in sxgbe_rx_dma_int_status()
325 static void sxgbe_dma_rx_watchdog(void __iomem *ioaddr, u32 riwt) in sxgbe_dma_rx_watchdog() argument
331 ioaddr + SXGBE_DMA_CHA_INT_RXWATCHTMR_REG(que_num)); in sxgbe_dma_rx_watchdog()
335 static void sxgbe_enable_tso(void __iomem *ioaddr, u8 chan_num) in sxgbe_enable_tso() argument
339 ctrl = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(chan_num)); in sxgbe_enable_tso()
341 writel(ctrl, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(chan_num)); in sxgbe_enable_tso()