Lines Matching refs:tx_queues_cfg
441 plat->tx_queues_cfg[0].use_prio = false; in common_default_data()
490 plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; in intel_mgbe_common_data()
493 plat->tx_queues_cfg[i].use_prio = false; in intel_mgbe_common_data()
496 plat->tx_queues_cfg[i].tbs_en = 1; in intel_mgbe_common_data()
504 plat->tx_queues_cfg[0].weight = 0x09; in intel_mgbe_common_data()
505 plat->tx_queues_cfg[1].weight = 0x0A; in intel_mgbe_common_data()
506 plat->tx_queues_cfg[2].weight = 0x0B; in intel_mgbe_common_data()
507 plat->tx_queues_cfg[3].weight = 0x0C; in intel_mgbe_common_data()
508 plat->tx_queues_cfg[4].weight = 0x0D; in intel_mgbe_common_data()
509 plat->tx_queues_cfg[5].weight = 0x0E; in intel_mgbe_common_data()
510 plat->tx_queues_cfg[6].weight = 0x0F; in intel_mgbe_common_data()
511 plat->tx_queues_cfg[7].weight = 0x10; in intel_mgbe_common_data()