Lines Matching refs:plat
91 int (*dwmac_set_phy_interface)(struct mediatek_dwmac_plat_data *plat);
92 int (*dwmac_set_delay)(struct mediatek_dwmac_plat_data *plat);
112 static int mt2712_set_interface(struct mediatek_dwmac_plat_data *plat) in mt2712_set_interface() argument
114 int rmii_clk_from_mac = plat->rmii_clk_from_mac ? RMII_CLK_SRC_INTERNAL : 0; in mt2712_set_interface()
115 int rmii_rxc = plat->rmii_rxc ? RMII_CLK_SRC_RXC : 0; in mt2712_set_interface()
119 switch (plat->phy_mode) { in mt2712_set_interface()
133 dev_err(plat->dev, "phy interface not supported\n"); in mt2712_set_interface()
137 regmap_write(plat->peri_regmap, PERI_ETH_PHY_INTF_SEL, intf_val); in mt2712_set_interface()
142 static void mt2712_delay_ps2stage(struct mediatek_dwmac_plat_data *plat) in mt2712_delay_ps2stage() argument
144 struct mac_delay_struct *mac_delay = &plat->mac_delay; in mt2712_delay_ps2stage()
146 switch (plat->phy_mode) { in mt2712_delay_ps2stage()
162 dev_err(plat->dev, "phy interface not supported\n"); in mt2712_delay_ps2stage()
167 static void mt2712_delay_stage2ps(struct mediatek_dwmac_plat_data *plat) in mt2712_delay_stage2ps() argument
169 struct mac_delay_struct *mac_delay = &plat->mac_delay; in mt2712_delay_stage2ps()
171 switch (plat->phy_mode) { in mt2712_delay_stage2ps()
187 dev_err(plat->dev, "phy interface not supported\n"); in mt2712_delay_stage2ps()
192 static int mt2712_set_delay(struct mediatek_dwmac_plat_data *plat) in mt2712_set_delay() argument
194 struct mac_delay_struct *mac_delay = &plat->mac_delay; in mt2712_set_delay()
197 mt2712_delay_ps2stage(plat); in mt2712_set_delay()
199 switch (plat->phy_mode) { in mt2712_set_delay()
210 if (plat->rmii_clk_from_mac) { in mt2712_set_delay()
230 if (plat->rmii_rxc) { in mt2712_set_delay()
270 dev_err(plat->dev, "phy interface not supported\n"); in mt2712_set_delay()
273 regmap_write(plat->peri_regmap, PERI_ETH_DLY, delay_val); in mt2712_set_delay()
274 regmap_write(plat->peri_regmap, PERI_ETH_DLY_FINE, fine_val); in mt2712_set_delay()
276 mt2712_delay_stage2ps(plat); in mt2712_set_delay()
291 static int mt8195_set_interface(struct mediatek_dwmac_plat_data *plat) in mt8195_set_interface() argument
293 int rmii_clk_from_mac = plat->rmii_clk_from_mac ? MT8195_RMII_CLK_SRC_INTERNAL : 0; in mt8195_set_interface()
294 int rmii_rxc = plat->rmii_rxc ? MT8195_RMII_CLK_SRC_RXC : 0; in mt8195_set_interface()
298 switch (plat->phy_mode) { in mt8195_set_interface()
313 dev_err(plat->dev, "phy interface not supported\n"); in mt8195_set_interface()
320 regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL0, intf_val); in mt8195_set_interface()
325 static void mt8195_delay_ps2stage(struct mediatek_dwmac_plat_data *plat) in mt8195_delay_ps2stage() argument
327 struct mac_delay_struct *mac_delay = &plat->mac_delay; in mt8195_delay_ps2stage()
334 static void mt8195_delay_stage2ps(struct mediatek_dwmac_plat_data *plat) in mt8195_delay_stage2ps() argument
336 struct mac_delay_struct *mac_delay = &plat->mac_delay; in mt8195_delay_stage2ps()
343 static int mt8195_set_delay(struct mediatek_dwmac_plat_data *plat) in mt8195_set_delay() argument
345 struct mac_delay_struct *mac_delay = &plat->mac_delay; in mt8195_set_delay()
348 mt8195_delay_ps2stage(plat); in mt8195_set_delay()
350 switch (plat->phy_mode) { in mt8195_set_delay()
361 if (plat->rmii_clk_from_mac) { in mt8195_set_delay()
387 if (plat->rmii_rxc) { in mt8195_set_delay()
426 dev_err(plat->dev, "phy interface not supported\n"); in mt8195_set_delay()
430 regmap_update_bits(plat->peri_regmap, in mt8195_set_delay()
437 regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL1, delay_val); in mt8195_set_delay()
438 regmap_write(plat->peri_regmap, MT8195_PERI_ETH_CTRL2, rmii_delay_val); in mt8195_set_delay()
440 mt8195_delay_stage2ps(plat); in mt8195_set_delay()
455 static int mediatek_dwmac_config_dt(struct mediatek_dwmac_plat_data *plat) in mediatek_dwmac_config_dt() argument
457 struct mac_delay_struct *mac_delay = &plat->mac_delay; in mediatek_dwmac_config_dt()
461 plat->peri_regmap = syscon_regmap_lookup_by_phandle(plat->np, "mediatek,pericfg"); in mediatek_dwmac_config_dt()
462 if (IS_ERR(plat->peri_regmap)) { in mediatek_dwmac_config_dt()
463 dev_err(plat->dev, "Failed to get pericfg syscon\n"); in mediatek_dwmac_config_dt()
464 return PTR_ERR(plat->peri_regmap); in mediatek_dwmac_config_dt()
467 err = of_get_phy_mode(plat->np, &plat->phy_mode); in mediatek_dwmac_config_dt()
469 dev_err(plat->dev, "not find phy-mode\n"); in mediatek_dwmac_config_dt()
473 if (!of_property_read_u32(plat->np, "mediatek,tx-delay-ps", &tx_delay_ps)) { in mediatek_dwmac_config_dt()
474 if (tx_delay_ps < plat->variant->tx_delay_max) { in mediatek_dwmac_config_dt()
477 dev_err(plat->dev, "Invalid TX clock delay: %dps\n", tx_delay_ps); in mediatek_dwmac_config_dt()
482 if (!of_property_read_u32(plat->np, "mediatek,rx-delay-ps", &rx_delay_ps)) { in mediatek_dwmac_config_dt()
483 if (rx_delay_ps < plat->variant->rx_delay_max) { in mediatek_dwmac_config_dt()
486 dev_err(plat->dev, "Invalid RX clock delay: %dps\n", rx_delay_ps); in mediatek_dwmac_config_dt()
491 mac_delay->tx_inv = of_property_read_bool(plat->np, "mediatek,txc-inverse"); in mediatek_dwmac_config_dt()
492 mac_delay->rx_inv = of_property_read_bool(plat->np, "mediatek,rxc-inverse"); in mediatek_dwmac_config_dt()
493 plat->rmii_rxc = of_property_read_bool(plat->np, "mediatek,rmii-rxc"); in mediatek_dwmac_config_dt()
494 plat->rmii_clk_from_mac = of_property_read_bool(plat->np, "mediatek,rmii-clk-from-mac"); in mediatek_dwmac_config_dt()
495 plat->mac_wol = of_property_read_bool(plat->np, "mediatek,mac-wol"); in mediatek_dwmac_config_dt()
500 static int mediatek_dwmac_clk_init(struct mediatek_dwmac_plat_data *plat) in mediatek_dwmac_clk_init() argument
502 const struct mediatek_dwmac_variant *variant = plat->variant; in mediatek_dwmac_clk_init()
505 plat->clks = devm_kcalloc(plat->dev, variant->num_clks, sizeof(*plat->clks), GFP_KERNEL); in mediatek_dwmac_clk_init()
506 if (!plat->clks) in mediatek_dwmac_clk_init()
510 plat->clks[i].id = variant->clk_list[i]; in mediatek_dwmac_clk_init()
512 ret = devm_clk_bulk_get(plat->dev, variant->num_clks, plat->clks); in mediatek_dwmac_clk_init()
522 if (plat->rmii_clk_from_mac) { in mediatek_dwmac_clk_init()
523 plat->rmii_internal_clk = devm_clk_get(plat->dev, "rmii_internal"); in mediatek_dwmac_clk_init()
524 if (IS_ERR(plat->rmii_internal_clk)) in mediatek_dwmac_clk_init()
525 ret = PTR_ERR(plat->rmii_internal_clk); in mediatek_dwmac_clk_init()
527 plat->rmii_internal_clk = NULL; in mediatek_dwmac_clk_init()
535 struct mediatek_dwmac_plat_data *plat = priv; in mediatek_dwmac_init() local
536 const struct mediatek_dwmac_variant *variant = plat->variant; in mediatek_dwmac_init()
540 ret = variant->dwmac_set_phy_interface(plat); in mediatek_dwmac_init()
542 dev_err(plat->dev, "failed to set phy interface, err = %d\n", ret); in mediatek_dwmac_init()
548 ret = variant->dwmac_set_delay(plat); in mediatek_dwmac_init()
550 dev_err(plat->dev, "failed to set delay value, err = %d\n", ret); in mediatek_dwmac_init()
560 struct mediatek_dwmac_plat_data *plat = priv; in mediatek_dwmac_clks_config() local
561 const struct mediatek_dwmac_variant *variant = plat->variant; in mediatek_dwmac_clks_config()
565 ret = clk_bulk_prepare_enable(variant->num_clks, plat->clks); in mediatek_dwmac_clks_config()
567 dev_err(plat->dev, "failed to enable clks, err = %d\n", ret); in mediatek_dwmac_clks_config()
571 ret = clk_prepare_enable(plat->rmii_internal_clk); in mediatek_dwmac_clks_config()
573 dev_err(plat->dev, "failed to enable rmii internal clk, err = %d\n", ret); in mediatek_dwmac_clks_config()
577 clk_disable_unprepare(plat->rmii_internal_clk); in mediatek_dwmac_clks_config()
578 clk_bulk_disable_unprepare(variant->num_clks, plat->clks); in mediatek_dwmac_clks_config()
585 struct plat_stmmacenet_data *plat, in mediatek_dwmac_common_data() argument
590 plat->interface = priv_plat->phy_mode; in mediatek_dwmac_common_data()
591 plat->use_phy_wol = priv_plat->mac_wol ? 0 : 1; in mediatek_dwmac_common_data()
592 plat->riwt_off = 1; in mediatek_dwmac_common_data()
593 plat->maxmtu = ETH_DATA_LEN; in mediatek_dwmac_common_data()
594 plat->addr64 = priv_plat->variant->dma_bit_mask; in mediatek_dwmac_common_data()
595 plat->bsp_priv = priv_plat; in mediatek_dwmac_common_data()
596 plat->init = mediatek_dwmac_init; in mediatek_dwmac_common_data()
597 plat->clks_config = mediatek_dwmac_clks_config; in mediatek_dwmac_common_data()
599 plat->safety_feat_cfg = devm_kzalloc(&pdev->dev, in mediatek_dwmac_common_data()
600 sizeof(*plat->safety_feat_cfg), in mediatek_dwmac_common_data()
602 if (!plat->safety_feat_cfg) in mediatek_dwmac_common_data()
605 plat->safety_feat_cfg->tsoee = 1; in mediatek_dwmac_common_data()
606 plat->safety_feat_cfg->mrxpee = 0; in mediatek_dwmac_common_data()
607 plat->safety_feat_cfg->mestee = 1; in mediatek_dwmac_common_data()
608 plat->safety_feat_cfg->mrxee = 1; in mediatek_dwmac_common_data()
609 plat->safety_feat_cfg->mtxee = 1; in mediatek_dwmac_common_data()
610 plat->safety_feat_cfg->epsi = 0; in mediatek_dwmac_common_data()
611 plat->safety_feat_cfg->edpp = 1; in mediatek_dwmac_common_data()
612 plat->safety_feat_cfg->prtyen = 1; in mediatek_dwmac_common_data()
613 plat->safety_feat_cfg->tmouten = 1; in mediatek_dwmac_common_data()
615 for (i = 0; i < plat->tx_queues_to_use; i++) { in mediatek_dwmac_common_data()
618 plat->tx_queues_cfg[i].tbs_en = 1; in mediatek_dwmac_common_data()