Lines Matching refs:ioaddr
15 int dwmac4_dma_reset(void __iomem *ioaddr) in dwmac4_dma_reset() argument
17 u32 value = readl(ioaddr + DMA_BUS_MODE); in dwmac4_dma_reset()
21 writel(value, ioaddr + DMA_BUS_MODE); in dwmac4_dma_reset()
23 return readl_poll_timeout(ioaddr + DMA_BUS_MODE, value, in dwmac4_dma_reset()
28 void dwmac4_set_rx_tail_ptr(void __iomem *ioaddr, u32 tail_ptr, u32 chan) in dwmac4_set_rx_tail_ptr() argument
30 writel(tail_ptr, ioaddr + DMA_CHAN_RX_END_ADDR(chan)); in dwmac4_set_rx_tail_ptr()
33 void dwmac4_set_tx_tail_ptr(void __iomem *ioaddr, u32 tail_ptr, u32 chan) in dwmac4_set_tx_tail_ptr() argument
35 writel(tail_ptr, ioaddr + DMA_CHAN_TX_END_ADDR(chan)); in dwmac4_set_tx_tail_ptr()
38 void dwmac4_dma_start_tx(void __iomem *ioaddr, u32 chan) in dwmac4_dma_start_tx() argument
40 u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_dma_start_tx()
43 writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_dma_start_tx()
45 value = readl(ioaddr + GMAC_CONFIG); in dwmac4_dma_start_tx()
47 writel(value, ioaddr + GMAC_CONFIG); in dwmac4_dma_start_tx()
50 void dwmac4_dma_stop_tx(void __iomem *ioaddr, u32 chan) in dwmac4_dma_stop_tx() argument
52 u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_dma_stop_tx()
55 writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_dma_stop_tx()
58 void dwmac4_dma_start_rx(void __iomem *ioaddr, u32 chan) in dwmac4_dma_start_rx() argument
60 u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan)); in dwmac4_dma_start_rx()
64 writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan)); in dwmac4_dma_start_rx()
66 value = readl(ioaddr + GMAC_CONFIG); in dwmac4_dma_start_rx()
68 writel(value, ioaddr + GMAC_CONFIG); in dwmac4_dma_start_rx()
71 void dwmac4_dma_stop_rx(void __iomem *ioaddr, u32 chan) in dwmac4_dma_stop_rx() argument
73 u32 value = readl(ioaddr + DMA_CHAN_RX_CONTROL(chan)); in dwmac4_dma_stop_rx()
76 writel(value, ioaddr + DMA_CHAN_RX_CONTROL(chan)); in dwmac4_dma_stop_rx()
79 void dwmac4_set_tx_ring_len(void __iomem *ioaddr, u32 len, u32 chan) in dwmac4_set_tx_ring_len() argument
81 writel(len, ioaddr + DMA_CHAN_TX_RING_LEN(chan)); in dwmac4_set_tx_ring_len()
84 void dwmac4_set_rx_ring_len(void __iomem *ioaddr, u32 len, u32 chan) in dwmac4_set_rx_ring_len() argument
86 writel(len, ioaddr + DMA_CHAN_RX_RING_LEN(chan)); in dwmac4_set_rx_ring_len()
89 void dwmac4_enable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx) in dwmac4_enable_dma_irq() argument
91 u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac4_enable_dma_irq()
98 writel(value, ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac4_enable_dma_irq()
101 void dwmac410_enable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx) in dwmac410_enable_dma_irq() argument
103 u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac410_enable_dma_irq()
110 writel(value, ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac410_enable_dma_irq()
113 void dwmac4_disable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx) in dwmac4_disable_dma_irq() argument
115 u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac4_disable_dma_irq()
122 writel(value, ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac4_disable_dma_irq()
125 void dwmac410_disable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx) in dwmac410_disable_dma_irq() argument
127 u32 value = readl(ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac410_disable_dma_irq()
134 writel(value, ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac410_disable_dma_irq()
137 int dwmac4_dma_interrupt(void __iomem *ioaddr, in dwmac4_dma_interrupt() argument
140 u32 intr_status = readl(ioaddr + DMA_CHAN_STATUS(chan)); in dwmac4_dma_interrupt()
141 u32 intr_en = readl(ioaddr + DMA_CHAN_INTR_ENA(chan)); in dwmac4_dma_interrupt()
186 writel(intr_status & intr_en, ioaddr + DMA_CHAN_STATUS(chan)); in dwmac4_dma_interrupt()
190 void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, const u8 addr[6], in stmmac_dwmac4_set_mac_addr() argument
201 writel(data | GMAC_HI_REG_AE, ioaddr + high); in stmmac_dwmac4_set_mac_addr()
203 writel(data, ioaddr + low); in stmmac_dwmac4_set_mac_addr()
207 void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable) in stmmac_dwmac4_set_mac() argument
209 u32 value = readl(ioaddr + GMAC_CONFIG); in stmmac_dwmac4_set_mac()
216 writel(value, ioaddr + GMAC_CONFIG); in stmmac_dwmac4_set_mac()
219 void stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, in stmmac_dwmac4_get_mac_addr() argument
225 hi_addr = readl(ioaddr + high); in stmmac_dwmac4_get_mac_addr()
226 lo_addr = readl(ioaddr + low); in stmmac_dwmac4_get_mac_addr()