Lines Matching refs:ioaddr

16 int dwmac_dma_reset(void __iomem *ioaddr)  in dwmac_dma_reset()  argument
18 u32 value = readl(ioaddr + DMA_BUS_MODE); in dwmac_dma_reset()
22 writel(value, ioaddr + DMA_BUS_MODE); in dwmac_dma_reset()
24 return readl_poll_timeout(ioaddr + DMA_BUS_MODE, value, in dwmac_dma_reset()
30 void dwmac_enable_dma_transmission(void __iomem *ioaddr) in dwmac_enable_dma_transmission() argument
32 writel(1, ioaddr + DMA_XMT_POLL_DEMAND); in dwmac_enable_dma_transmission()
35 void dwmac_enable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx) in dwmac_enable_dma_irq() argument
37 u32 value = readl(ioaddr + DMA_INTR_ENA); in dwmac_enable_dma_irq()
44 writel(value, ioaddr + DMA_INTR_ENA); in dwmac_enable_dma_irq()
47 void dwmac_disable_dma_irq(void __iomem *ioaddr, u32 chan, bool rx, bool tx) in dwmac_disable_dma_irq() argument
49 u32 value = readl(ioaddr + DMA_INTR_ENA); in dwmac_disable_dma_irq()
56 writel(value, ioaddr + DMA_INTR_ENA); in dwmac_disable_dma_irq()
59 void dwmac_dma_start_tx(void __iomem *ioaddr, u32 chan) in dwmac_dma_start_tx() argument
61 u32 value = readl(ioaddr + DMA_CONTROL); in dwmac_dma_start_tx()
63 writel(value, ioaddr + DMA_CONTROL); in dwmac_dma_start_tx()
66 void dwmac_dma_stop_tx(void __iomem *ioaddr, u32 chan) in dwmac_dma_stop_tx() argument
68 u32 value = readl(ioaddr + DMA_CONTROL); in dwmac_dma_stop_tx()
70 writel(value, ioaddr + DMA_CONTROL); in dwmac_dma_stop_tx()
73 void dwmac_dma_start_rx(void __iomem *ioaddr, u32 chan) in dwmac_dma_start_rx() argument
75 u32 value = readl(ioaddr + DMA_CONTROL); in dwmac_dma_start_rx()
77 writel(value, ioaddr + DMA_CONTROL); in dwmac_dma_start_rx()
80 void dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan) in dwmac_dma_stop_rx() argument
82 u32 value = readl(ioaddr + DMA_CONTROL); in dwmac_dma_stop_rx()
84 writel(value, ioaddr + DMA_CONTROL); in dwmac_dma_stop_rx()
157 int dwmac_dma_interrupt(void __iomem *ioaddr, in dwmac_dma_interrupt() argument
162 u32 intr_status = readl(ioaddr + DMA_STATUS); in dwmac_dma_interrupt()
209 u32 value = readl(ioaddr + DMA_INTR_ENA); in dwmac_dma_interrupt()
229 writel((intr_status & 0x1ffff), ioaddr + DMA_STATUS); in dwmac_dma_interrupt()
234 void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr) in dwmac_dma_flush_tx_fifo() argument
236 u32 csr6 = readl(ioaddr + DMA_CONTROL); in dwmac_dma_flush_tx_fifo()
237 writel((csr6 | DMA_CONTROL_FTF), ioaddr + DMA_CONTROL); in dwmac_dma_flush_tx_fifo()
239 do {} while ((readl(ioaddr + DMA_CONTROL) & DMA_CONTROL_FTF)); in dwmac_dma_flush_tx_fifo()
242 void stmmac_set_mac_addr(void __iomem *ioaddr, const u8 addr[6], in stmmac_set_mac_addr() argument
252 writel(data | GMAC_HI_REG_AE, ioaddr + high); in stmmac_set_mac_addr()
254 writel(data, ioaddr + low); in stmmac_set_mac_addr()
259 void stmmac_set_mac(void __iomem *ioaddr, bool enable) in stmmac_set_mac() argument
263 old_val = readl(ioaddr + MAC_CTRL_REG); in stmmac_set_mac()
272 writel(value, ioaddr + MAC_CTRL_REG); in stmmac_set_mac()
275 void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, in stmmac_get_mac_addr() argument
281 hi_addr = readl(ioaddr + high); in stmmac_get_mac_addr()
282 lo_addr = readl(ioaddr + low); in stmmac_get_mac_addr()