Lines Matching defs:value
13 u32 value = readl(ioaddr + XGMAC_DMA_MODE); in dwxgmac2_dma_reset() local
25 u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_init() local
39 u32 value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan)); in dwxgmac2_dma_init_chan() local
53 u32 value; in dwxgmac2_dma_init_rx_chan() local
69 u32 value; in dwxgmac2_dma_init_tx_chan() local
83 u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_axi() local
145 u32 value = readl(ioaddr + XGMAC_MTL_RXQ_OPMODE(channel)); in dwxgmac2_dma_rx_mode() local
211 u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel)); in dwxgmac2_dma_tx_mode() local
254 u32 value = readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan)); in dwxgmac2_enable_dma_irq() local
267 u32 value = readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan)); in dwxgmac2_disable_dma_irq() local
279 u32 value; in dwxgmac2_dma_start_tx() local
292 u32 value; in dwxgmac2_dma_stop_tx() local
305 u32 value; in dwxgmac2_dma_start_rx() local
318 u32 value; in dwxgmac2_dma_stop_rx() local
479 u32 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_enable_tso() local
491 u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel)); in dwxgmac2_qmode() local
508 u32 value; in dwxgmac2_set_bfsize() local
518 u32 value = readl(ioaddr + XGMAC_RX_CONFIG); in dwxgmac2_enable_sph() local
534 u32 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_enable_tbs() local