Lines Matching refs:ioaddr
11 static int dwxgmac2_dma_reset(void __iomem *ioaddr) in dwxgmac2_dma_reset() argument
13 u32 value = readl(ioaddr + XGMAC_DMA_MODE); in dwxgmac2_dma_reset()
16 writel(value | XGMAC_SWR, ioaddr + XGMAC_DMA_MODE); in dwxgmac2_dma_reset()
18 return readl_poll_timeout(ioaddr + XGMAC_DMA_MODE, value, in dwxgmac2_dma_reset()
22 static void dwxgmac2_dma_init(void __iomem *ioaddr, in dwxgmac2_dma_init() argument
25 u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_init()
33 writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_init()
36 static void dwxgmac2_dma_init_chan(void __iomem *ioaddr, in dwxgmac2_dma_init_chan() argument
39 u32 value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan)); in dwxgmac2_dma_init_chan()
44 writel(value, ioaddr + XGMAC_DMA_CH_CONTROL(chan)); in dwxgmac2_dma_init_chan()
45 writel(XGMAC_DMA_INT_DEFAULT_EN, ioaddr + XGMAC_DMA_CH_INT_EN(chan)); in dwxgmac2_dma_init_chan()
48 static void dwxgmac2_dma_init_rx_chan(void __iomem *ioaddr, in dwxgmac2_dma_init_rx_chan() argument
55 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); in dwxgmac2_dma_init_rx_chan()
58 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); in dwxgmac2_dma_init_rx_chan()
60 writel(upper_32_bits(phy), ioaddr + XGMAC_DMA_CH_RxDESC_HADDR(chan)); in dwxgmac2_dma_init_rx_chan()
61 writel(lower_32_bits(phy), ioaddr + XGMAC_DMA_CH_RxDESC_LADDR(chan)); in dwxgmac2_dma_init_rx_chan()
64 static void dwxgmac2_dma_init_tx_chan(void __iomem *ioaddr, in dwxgmac2_dma_init_tx_chan() argument
71 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_init_tx_chan()
75 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_init_tx_chan()
77 writel(upper_32_bits(phy), ioaddr + XGMAC_DMA_CH_TxDESC_HADDR(chan)); in dwxgmac2_dma_init_tx_chan()
78 writel(lower_32_bits(phy), ioaddr + XGMAC_DMA_CH_TxDESC_LADDR(chan)); in dwxgmac2_dma_init_tx_chan()
81 static void dwxgmac2_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) in dwxgmac2_dma_axi() argument
83 u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_axi()
129 writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_axi()
130 writel(XGMAC_TDPS, ioaddr + XGMAC_TX_EDMA_CTRL); in dwxgmac2_dma_axi()
131 writel(XGMAC_RDPS, ioaddr + XGMAC_RX_EDMA_CTRL); in dwxgmac2_dma_axi()
134 static void dwxgmac2_dma_dump_regs(void __iomem *ioaddr, u32 *reg_space) in dwxgmac2_dma_dump_regs() argument
139 reg_space[i] = readl(ioaddr + i * 4); in dwxgmac2_dma_dump_regs()
142 static void dwxgmac2_dma_rx_mode(void __iomem *ioaddr, int mode, in dwxgmac2_dma_rx_mode() argument
145 u32 value = readl(ioaddr + XGMAC_MTL_RXQ_OPMODE(channel)); in dwxgmac2_dma_rx_mode()
166 u32 flow = readl(ioaddr + XGMAC_MTL_RXQ_FLOW_CONTROL(channel)); in dwxgmac2_dma_rx_mode()
198 writel(flow, ioaddr + XGMAC_MTL_RXQ_FLOW_CONTROL(channel)); in dwxgmac2_dma_rx_mode()
201 writel(value, ioaddr + XGMAC_MTL_RXQ_OPMODE(channel)); in dwxgmac2_dma_rx_mode()
204 value = readl(ioaddr + XGMAC_MTL_QINTEN(channel)); in dwxgmac2_dma_rx_mode()
205 writel(value | XGMAC_RXOIE, ioaddr + XGMAC_MTL_QINTEN(channel)); in dwxgmac2_dma_rx_mode()
208 static void dwxgmac2_dma_tx_mode(void __iomem *ioaddr, int mode, in dwxgmac2_dma_tx_mode() argument
211 u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel)); in dwxgmac2_dma_tx_mode()
248 writel(value, ioaddr + XGMAC_MTL_TXQ_OPMODE(channel)); in dwxgmac2_dma_tx_mode()
251 static void dwxgmac2_enable_dma_irq(void __iomem *ioaddr, u32 chan, in dwxgmac2_enable_dma_irq() argument
254 u32 value = readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan)); in dwxgmac2_enable_dma_irq()
261 writel(value, ioaddr + XGMAC_DMA_CH_INT_EN(chan)); in dwxgmac2_enable_dma_irq()
264 static void dwxgmac2_disable_dma_irq(void __iomem *ioaddr, u32 chan, in dwxgmac2_disable_dma_irq() argument
267 u32 value = readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan)); in dwxgmac2_disable_dma_irq()
274 writel(value, ioaddr + XGMAC_DMA_CH_INT_EN(chan)); in dwxgmac2_disable_dma_irq()
277 static void dwxgmac2_dma_start_tx(void __iomem *ioaddr, u32 chan) in dwxgmac2_dma_start_tx() argument
281 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_start_tx()
283 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_start_tx()
285 value = readl(ioaddr + XGMAC_TX_CONFIG); in dwxgmac2_dma_start_tx()
287 writel(value, ioaddr + XGMAC_TX_CONFIG); in dwxgmac2_dma_start_tx()
290 static void dwxgmac2_dma_stop_tx(void __iomem *ioaddr, u32 chan) in dwxgmac2_dma_stop_tx() argument
294 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_stop_tx()
296 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_dma_stop_tx()
298 value = readl(ioaddr + XGMAC_TX_CONFIG); in dwxgmac2_dma_stop_tx()
300 writel(value, ioaddr + XGMAC_TX_CONFIG); in dwxgmac2_dma_stop_tx()
303 static void dwxgmac2_dma_start_rx(void __iomem *ioaddr, u32 chan) in dwxgmac2_dma_start_rx() argument
307 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); in dwxgmac2_dma_start_rx()
309 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); in dwxgmac2_dma_start_rx()
311 value = readl(ioaddr + XGMAC_RX_CONFIG); in dwxgmac2_dma_start_rx()
313 writel(value, ioaddr + XGMAC_RX_CONFIG); in dwxgmac2_dma_start_rx()
316 static void dwxgmac2_dma_stop_rx(void __iomem *ioaddr, u32 chan) in dwxgmac2_dma_stop_rx() argument
320 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); in dwxgmac2_dma_stop_rx()
322 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); in dwxgmac2_dma_stop_rx()
325 static int dwxgmac2_dma_interrupt(void __iomem *ioaddr, in dwxgmac2_dma_interrupt() argument
329 u32 intr_status = readl(ioaddr + XGMAC_DMA_CH_STATUS(chan)); in dwxgmac2_dma_interrupt()
330 u32 intr_en = readl(ioaddr + XGMAC_DMA_CH_INT_EN(chan)); in dwxgmac2_dma_interrupt()
369 writel(intr_en & intr_status, ioaddr + XGMAC_DMA_CH_STATUS(chan)); in dwxgmac2_dma_interrupt()
374 static int dwxgmac2_get_hw_feature(void __iomem *ioaddr, in dwxgmac2_get_hw_feature() argument
380 hw_cap = readl(ioaddr + XGMAC_HW_FEATURE0); in dwxgmac2_get_hw_feature()
396 hw_cap = readl(ioaddr + XGMAC_HW_FEATURE1); in dwxgmac2_get_hw_feature()
425 hw_cap = readl(ioaddr + XGMAC_HW_FEATURE2); in dwxgmac2_get_hw_feature()
437 hw_cap = readl(ioaddr + XGMAC_HW_FEATURE3); in dwxgmac2_get_hw_feature()
452 static void dwxgmac2_rx_watchdog(void __iomem *ioaddr, u32 riwt, u32 queue) in dwxgmac2_rx_watchdog() argument
454 writel(riwt & XGMAC_RWT, ioaddr + XGMAC_DMA_CH_Rx_WATCHDOG(queue)); in dwxgmac2_rx_watchdog()
457 static void dwxgmac2_set_rx_ring_len(void __iomem *ioaddr, u32 len, u32 chan) in dwxgmac2_set_rx_ring_len() argument
459 writel(len, ioaddr + XGMAC_DMA_CH_RxDESC_RING_LEN(chan)); in dwxgmac2_set_rx_ring_len()
462 static void dwxgmac2_set_tx_ring_len(void __iomem *ioaddr, u32 len, u32 chan) in dwxgmac2_set_tx_ring_len() argument
464 writel(len, ioaddr + XGMAC_DMA_CH_TxDESC_RING_LEN(chan)); in dwxgmac2_set_tx_ring_len()
467 static void dwxgmac2_set_rx_tail_ptr(void __iomem *ioaddr, u32 ptr, u32 chan) in dwxgmac2_set_rx_tail_ptr() argument
469 writel(ptr, ioaddr + XGMAC_DMA_CH_RxDESC_TAIL_LPTR(chan)); in dwxgmac2_set_rx_tail_ptr()
472 static void dwxgmac2_set_tx_tail_ptr(void __iomem *ioaddr, u32 ptr, u32 chan) in dwxgmac2_set_tx_tail_ptr() argument
474 writel(ptr, ioaddr + XGMAC_DMA_CH_TxDESC_TAIL_LPTR(chan)); in dwxgmac2_set_tx_tail_ptr()
477 static void dwxgmac2_enable_tso(void __iomem *ioaddr, bool en, u32 chan) in dwxgmac2_enable_tso() argument
479 u32 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_enable_tso()
486 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_enable_tso()
489 static void dwxgmac2_qmode(void __iomem *ioaddr, u32 channel, u8 qmode) in dwxgmac2_qmode() argument
491 u32 value = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE(channel)); in dwxgmac2_qmode()
492 u32 flow = readl(ioaddr + XGMAC_RX_FLOW_CTRL); in dwxgmac2_qmode()
497 writel(0, ioaddr + XGMAC_MTL_TCx_ETS_CONTROL(channel)); in dwxgmac2_qmode()
500 writel(flow & (~XGMAC_RFE), ioaddr + XGMAC_RX_FLOW_CTRL); in dwxgmac2_qmode()
503 writel(value, ioaddr + XGMAC_MTL_TXQ_OPMODE(channel)); in dwxgmac2_qmode()
506 static void dwxgmac2_set_bfsize(void __iomem *ioaddr, int bfsize, u32 chan) in dwxgmac2_set_bfsize() argument
510 value = readl(ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); in dwxgmac2_set_bfsize()
513 writel(value, ioaddr + XGMAC_DMA_CH_RX_CONTROL(chan)); in dwxgmac2_set_bfsize()
516 static void dwxgmac2_enable_sph(void __iomem *ioaddr, bool en, u32 chan) in dwxgmac2_enable_sph() argument
518 u32 value = readl(ioaddr + XGMAC_RX_CONFIG); in dwxgmac2_enable_sph()
522 writel(value, ioaddr + XGMAC_RX_CONFIG); in dwxgmac2_enable_sph()
524 value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan)); in dwxgmac2_enable_sph()
529 writel(value, ioaddr + XGMAC_DMA_CH_CONTROL(chan)); in dwxgmac2_enable_sph()
532 static int dwxgmac2_enable_tbs(void __iomem *ioaddr, bool en, u32 chan) in dwxgmac2_enable_tbs() argument
534 u32 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_enable_tbs()
541 writel(value, ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)); in dwxgmac2_enable_tbs()
543 value = readl(ioaddr + XGMAC_DMA_CH_TX_CONTROL(chan)) & XGMAC_EDSE; in dwxgmac2_enable_tbs()
547 writel(XGMAC_DEF_FTOS, ioaddr + XGMAC_DMA_TBS_CTRL0); in dwxgmac2_enable_tbs()
548 writel(XGMAC_DEF_FTOS, ioaddr + XGMAC_DMA_TBS_CTRL1); in dwxgmac2_enable_tbs()
549 writel(XGMAC_DEF_FTOS, ioaddr + XGMAC_DMA_TBS_CTRL2); in dwxgmac2_enable_tbs()
550 writel(XGMAC_DEF_FTOS, ioaddr + XGMAC_DMA_TBS_CTRL3); in dwxgmac2_enable_tbs()