Lines Matching refs:regval
38 u32 regval; in xlgmac_disable_rx_csum() local
40 regval = readl(pdata->mac_regs + MAC_RCR); in xlgmac_disable_rx_csum()
41 regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_IPC_POS, in xlgmac_disable_rx_csum()
43 writel(regval, pdata->mac_regs + MAC_RCR); in xlgmac_disable_rx_csum()
50 u32 regval; in xlgmac_enable_rx_csum() local
52 regval = readl(pdata->mac_regs + MAC_RCR); in xlgmac_enable_rx_csum()
53 regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_IPC_POS, in xlgmac_enable_rx_csum()
55 writel(regval, pdata->mac_regs + MAC_RCR); in xlgmac_enable_rx_csum()
112 u32 regval; in xlgmac_enable_rx_vlan_stripping() local
114 regval = readl(pdata->mac_regs + MAC_VLANTR); in xlgmac_enable_rx_vlan_stripping()
116 regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_EVLRXS_POS, in xlgmac_enable_rx_vlan_stripping()
119 regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_DOVLTC_POS, in xlgmac_enable_rx_vlan_stripping()
122 regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_ERSVLM_POS, in xlgmac_enable_rx_vlan_stripping()
125 regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_ESVL_POS, in xlgmac_enable_rx_vlan_stripping()
128 regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_EVLS_POS, in xlgmac_enable_rx_vlan_stripping()
130 writel(regval, pdata->mac_regs + MAC_VLANTR); in xlgmac_enable_rx_vlan_stripping()
137 u32 regval; in xlgmac_disable_rx_vlan_stripping() local
139 regval = readl(pdata->mac_regs + MAC_VLANTR); in xlgmac_disable_rx_vlan_stripping()
140 regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_EVLS_POS, in xlgmac_disable_rx_vlan_stripping()
142 writel(regval, pdata->mac_regs + MAC_VLANTR); in xlgmac_disable_rx_vlan_stripping()
149 u32 regval; in xlgmac_enable_rx_vlan_filtering() local
151 regval = readl(pdata->mac_regs + MAC_PFR); in xlgmac_enable_rx_vlan_filtering()
153 regval = XLGMAC_SET_REG_BITS(regval, MAC_PFR_VTFE_POS, in xlgmac_enable_rx_vlan_filtering()
155 writel(regval, pdata->mac_regs + MAC_PFR); in xlgmac_enable_rx_vlan_filtering()
157 regval = readl(pdata->mac_regs + MAC_VLANTR); in xlgmac_enable_rx_vlan_filtering()
159 regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_VTHM_POS, in xlgmac_enable_rx_vlan_filtering()
162 regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_VTIM_POS, in xlgmac_enable_rx_vlan_filtering()
165 regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_ETV_POS, in xlgmac_enable_rx_vlan_filtering()
173 regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANTR_VL_POS, in xlgmac_enable_rx_vlan_filtering()
175 writel(regval, pdata->mac_regs + MAC_VLANTR); in xlgmac_enable_rx_vlan_filtering()
182 u32 regval; in xlgmac_disable_rx_vlan_filtering() local
184 regval = readl(pdata->mac_regs + MAC_PFR); in xlgmac_disable_rx_vlan_filtering()
186 regval = XLGMAC_SET_REG_BITS(regval, MAC_PFR_VTFE_POS, in xlgmac_disable_rx_vlan_filtering()
188 writel(regval, pdata->mac_regs + MAC_PFR); in xlgmac_disable_rx_vlan_filtering()
221 u32 regval; in xlgmac_update_vlan_hash_table() local
234 regval = readl(pdata->mac_regs + MAC_VLANHTR); in xlgmac_update_vlan_hash_table()
236 regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANHTR_VLHT_POS, in xlgmac_update_vlan_hash_table()
238 writel(regval, pdata->mac_regs + MAC_VLANHTR); in xlgmac_update_vlan_hash_table()
247 u32 regval; in xlgmac_set_promiscuous_mode() local
249 regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_PFR), in xlgmac_set_promiscuous_mode()
251 if (regval == val) in xlgmac_set_promiscuous_mode()
257 regval = readl(pdata->mac_regs + MAC_PFR); in xlgmac_set_promiscuous_mode()
258 regval = XLGMAC_SET_REG_BITS(regval, MAC_PFR_PR_POS, in xlgmac_set_promiscuous_mode()
260 writel(regval, pdata->mac_regs + MAC_PFR); in xlgmac_set_promiscuous_mode()
277 u32 regval; in xlgmac_set_all_multicast_mode() local
279 regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_PFR), in xlgmac_set_all_multicast_mode()
281 if (regval == val) in xlgmac_set_all_multicast_mode()
287 regval = readl(pdata->mac_regs + MAC_PFR); in xlgmac_set_all_multicast_mode()
288 regval = XLGMAC_SET_REG_BITS(regval, MAC_PFR_PM_POS, in xlgmac_set_all_multicast_mode()
290 writel(regval, pdata->mac_regs + MAC_PFR); in xlgmac_set_all_multicast_mode()
375 u32 regval; in xlgmac_config_mac_address() local
381 regval = readl(pdata->mac_regs + MAC_PFR); in xlgmac_config_mac_address()
382 regval = XLGMAC_SET_REG_BITS(regval, MAC_PFR_HPF_POS, in xlgmac_config_mac_address()
384 regval = XLGMAC_SET_REG_BITS(regval, MAC_PFR_HUC_POS, in xlgmac_config_mac_address()
386 regval = XLGMAC_SET_REG_BITS(regval, MAC_PFR_HMC_POS, in xlgmac_config_mac_address()
388 writel(regval, pdata->mac_regs + MAC_PFR); in xlgmac_config_mac_address()
395 u32 regval; in xlgmac_config_jumbo_enable() local
399 regval = readl(pdata->mac_regs + MAC_RCR); in xlgmac_config_jumbo_enable()
400 regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_JE_POS, in xlgmac_config_jumbo_enable()
402 writel(regval, pdata->mac_regs + MAC_RCR); in xlgmac_config_jumbo_enable()
415 u32 regval; in xlgmac_config_vlan_support() local
417 regval = readl(pdata->mac_regs + MAC_VLANIR); in xlgmac_config_vlan_support()
419 regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANIR_CSVL_POS, in xlgmac_config_vlan_support()
421 regval = XLGMAC_SET_REG_BITS(regval, MAC_VLANIR_VLTI_POS, in xlgmac_config_vlan_support()
423 writel(regval, pdata->mac_regs + MAC_VLANIR); in xlgmac_config_vlan_support()
501 u32 regval; in xlgmac_enable_tx() local
509 regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_TCR)); in xlgmac_enable_tx()
510 regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_TCR_ST_POS, in xlgmac_enable_tx()
512 writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_TCR)); in xlgmac_enable_tx()
517 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR)); in xlgmac_enable_tx()
518 regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_TQOMR_TXQEN_POS, in xlgmac_enable_tx()
521 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR)); in xlgmac_enable_tx()
525 regval = readl(pdata->mac_regs + MAC_TCR); in xlgmac_enable_tx()
526 regval = XLGMAC_SET_REG_BITS(regval, MAC_TCR_TE_POS, in xlgmac_enable_tx()
528 writel(regval, pdata->mac_regs + MAC_TCR); in xlgmac_enable_tx()
535 u32 regval; in xlgmac_disable_tx() local
547 regval = readl(pdata->mac_regs + MAC_TCR); in xlgmac_disable_tx()
548 regval = XLGMAC_SET_REG_BITS(regval, MAC_TCR_TE_POS, in xlgmac_disable_tx()
550 writel(regval, pdata->mac_regs + MAC_TCR); in xlgmac_disable_tx()
554 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR)); in xlgmac_disable_tx()
555 regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_TQOMR_TXQEN_POS, in xlgmac_disable_tx()
557 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR)); in xlgmac_disable_tx()
566 regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_TCR)); in xlgmac_disable_tx()
567 regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_TCR_ST_POS, in xlgmac_disable_tx()
569 writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_TCR)); in xlgmac_disable_tx()
605 unsigned int regval, i; in xlgmac_enable_rx() local
613 regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_RCR)); in xlgmac_enable_rx()
614 regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_RCR_SR_POS, in xlgmac_enable_rx()
616 writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_RCR)); in xlgmac_enable_rx()
620 regval = 0; in xlgmac_enable_rx()
622 regval |= (0x02 << (i << 1)); in xlgmac_enable_rx()
623 writel(regval, pdata->mac_regs + MAC_RQC0R); in xlgmac_enable_rx()
626 regval = readl(pdata->mac_regs + MAC_RCR); in xlgmac_enable_rx()
627 regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_DCRCC_POS, in xlgmac_enable_rx()
629 regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_CST_POS, in xlgmac_enable_rx()
631 regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_ACS_POS, in xlgmac_enable_rx()
633 regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_RE_POS, in xlgmac_enable_rx()
635 writel(regval, pdata->mac_regs + MAC_RCR); in xlgmac_enable_rx()
642 u32 regval; in xlgmac_disable_rx() local
645 regval = readl(pdata->mac_regs + MAC_RCR); in xlgmac_disable_rx()
646 regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_DCRCC_POS, in xlgmac_disable_rx()
648 regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_CST_POS, in xlgmac_disable_rx()
650 regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_ACS_POS, in xlgmac_disable_rx()
652 regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_RE_POS, in xlgmac_disable_rx()
654 writel(regval, pdata->mac_regs + MAC_RCR); in xlgmac_disable_rx()
669 regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_RCR)); in xlgmac_disable_rx()
670 regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_RCR_SR_POS, in xlgmac_disable_rx()
672 writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_RCR)); in xlgmac_disable_rx()
1191 unsigned int reg, regval; in xlgmac_disable_tx_flow_control() local
1196 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); in xlgmac_disable_tx_flow_control()
1197 regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQOMR_EHFC_POS, in xlgmac_disable_tx_flow_control()
1199 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); in xlgmac_disable_tx_flow_control()
1207 regval = readl(pdata->mac_regs + reg); in xlgmac_disable_tx_flow_control()
1208 regval = XLGMAC_SET_REG_BITS(regval, in xlgmac_disable_tx_flow_control()
1212 writel(regval, pdata->mac_regs + reg); in xlgmac_disable_tx_flow_control()
1223 unsigned int reg, regval; in xlgmac_enable_tx_flow_control() local
1228 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); in xlgmac_enable_tx_flow_control()
1229 regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQOMR_EHFC_POS, in xlgmac_enable_tx_flow_control()
1231 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); in xlgmac_enable_tx_flow_control()
1239 regval = readl(pdata->mac_regs + reg); in xlgmac_enable_tx_flow_control()
1242 regval = XLGMAC_SET_REG_BITS(regval, MAC_Q0TFCR_TFE_POS, in xlgmac_enable_tx_flow_control()
1245 regval = XLGMAC_SET_REG_BITS(regval, MAC_Q0TFCR_PT_POS, in xlgmac_enable_tx_flow_control()
1248 writel(regval, pdata->mac_regs + reg); in xlgmac_enable_tx_flow_control()
1258 u32 regval; in xlgmac_disable_rx_flow_control() local
1260 regval = readl(pdata->mac_regs + MAC_RFCR); in xlgmac_disable_rx_flow_control()
1261 regval = XLGMAC_SET_REG_BITS(regval, MAC_RFCR_RFE_POS, in xlgmac_disable_rx_flow_control()
1263 writel(regval, pdata->mac_regs + MAC_RFCR); in xlgmac_disable_rx_flow_control()
1270 u32 regval; in xlgmac_enable_rx_flow_control() local
1272 regval = readl(pdata->mac_regs + MAC_RFCR); in xlgmac_enable_rx_flow_control()
1273 regval = XLGMAC_SET_REG_BITS(regval, MAC_RFCR_RFE_POS, in xlgmac_enable_rx_flow_control()
1275 writel(regval, pdata->mac_regs + MAC_RFCR); in xlgmac_enable_rx_flow_control()
1304 u32 regval; in xlgmac_config_rx_coalesce() local
1311 regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_RIWT)); in xlgmac_config_rx_coalesce()
1312 regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_RIWT_RWT_POS, in xlgmac_config_rx_coalesce()
1315 writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_RIWT)); in xlgmac_config_rx_coalesce()
1330 u32 regval; in xlgmac_config_rx_fep_enable() local
1333 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); in xlgmac_config_rx_fep_enable()
1334 regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQOMR_FEP_POS, in xlgmac_config_rx_fep_enable()
1336 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); in xlgmac_config_rx_fep_enable()
1343 u32 regval; in xlgmac_config_rx_fup_enable() local
1346 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); in xlgmac_config_rx_fup_enable()
1347 regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQOMR_FUP_POS, in xlgmac_config_rx_fup_enable()
1349 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); in xlgmac_config_rx_fup_enable()
1362 u32 regval; in xlgmac_config_rx_buffer_size() local
1369 regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_RCR)); in xlgmac_config_rx_buffer_size()
1370 regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_RCR_RBSZ_POS, in xlgmac_config_rx_buffer_size()
1373 writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_RCR)); in xlgmac_config_rx_buffer_size()
1381 u32 regval; in xlgmac_config_tso_mode() local
1389 regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_TCR)); in xlgmac_config_tso_mode()
1390 regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_TCR_TSE_POS, in xlgmac_config_tso_mode()
1392 writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_TCR)); in xlgmac_config_tso_mode()
1401 u32 regval; in xlgmac_config_sph_mode() local
1408 regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_CR)); in xlgmac_config_sph_mode()
1409 regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_CR_SPH_POS, in xlgmac_config_sph_mode()
1411 writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_CR)); in xlgmac_config_sph_mode()
1414 regval = readl(pdata->mac_regs + MAC_RCR); in xlgmac_config_sph_mode()
1415 regval = XLGMAC_SET_REG_BITS(regval, MAC_RCR_HDSMS_POS, in xlgmac_config_sph_mode()
1418 writel(regval, pdata->mac_regs + MAC_RCR); in xlgmac_config_sph_mode()
1461 u32 regval; in xlgmac_config_rx_threshold() local
1464 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); in xlgmac_config_rx_threshold()
1465 regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQOMR_RTC_POS, in xlgmac_config_rx_threshold()
1467 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); in xlgmac_config_rx_threshold()
1476 u32 regval; in xlgmac_config_mtl_mode() local
1479 regval = readl(pdata->mac_regs + MTL_OMR); in xlgmac_config_mtl_mode()
1480 regval = XLGMAC_SET_REG_BITS(regval, MTL_OMR_ETSALG_POS, in xlgmac_config_mtl_mode()
1482 writel(regval, pdata->mac_regs + MTL_OMR); in xlgmac_config_mtl_mode()
1486 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_TC_ETSCR)); in xlgmac_config_mtl_mode()
1487 regval = XLGMAC_SET_REG_BITS(regval, MTL_TC_ETSCR_TSA_POS, in xlgmac_config_mtl_mode()
1489 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_TC_ETSCR)); in xlgmac_config_mtl_mode()
1491 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_TC_QWR)); in xlgmac_config_mtl_mode()
1492 regval = XLGMAC_SET_REG_BITS(regval, MTL_TC_QWR_QW_POS, in xlgmac_config_mtl_mode()
1494 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_TC_QWR)); in xlgmac_config_mtl_mode()
1498 regval = readl(pdata->mac_regs + MTL_OMR); in xlgmac_config_mtl_mode()
1499 regval = XLGMAC_SET_REG_BITS(regval, MTL_OMR_RAA_POS, in xlgmac_config_mtl_mode()
1501 writel(regval, pdata->mac_regs + MTL_OMR); in xlgmac_config_mtl_mode()
1508 unsigned int reg, regval; in xlgmac_config_queue_mapping() local
1522 regval = readl(XLGMAC_MTL_REG(pdata, queue, in xlgmac_config_queue_mapping()
1524 regval = XLGMAC_SET_REG_BITS(regval, in xlgmac_config_queue_mapping()
1528 writel(regval, XLGMAC_MTL_REG(pdata, queue, in xlgmac_config_queue_mapping()
1536 regval = readl(XLGMAC_MTL_REG(pdata, queue, in xlgmac_config_queue_mapping()
1538 regval = XLGMAC_SET_REG_BITS(regval, in xlgmac_config_queue_mapping()
1542 writel(regval, XLGMAC_MTL_REG(pdata, queue, in xlgmac_config_queue_mapping()
1555 regval = 0; in xlgmac_config_queue_mapping()
1572 regval |= (mask << ((i++ % MAC_RQC2_Q_PER_REG) << 3)); in xlgmac_config_queue_mapping()
1577 writel(regval, pdata->mac_regs + reg); in xlgmac_config_queue_mapping()
1579 regval = 0; in xlgmac_config_queue_mapping()
1586 regval = readl(pdata->mac_regs + reg); in xlgmac_config_queue_mapping()
1587 regval |= (MTL_RQDCM0R_Q0MDMACH | MTL_RQDCM0R_Q1MDMACH | in xlgmac_config_queue_mapping()
1589 writel(regval, pdata->mac_regs + reg); in xlgmac_config_queue_mapping()
1592 regval = readl(pdata->mac_regs + reg); in xlgmac_config_queue_mapping()
1593 regval |= (MTL_RQDCM1R_Q4MDMACH | MTL_RQDCM1R_Q5MDMACH | in xlgmac_config_queue_mapping()
1595 writel(regval, pdata->mac_regs + reg); in xlgmac_config_queue_mapping()
1598 regval = readl(pdata->mac_regs + reg); in xlgmac_config_queue_mapping()
1599 regval |= (MTL_RQDCM2R_Q8MDMACH | MTL_RQDCM2R_Q9MDMACH | in xlgmac_config_queue_mapping()
1601 writel(regval, pdata->mac_regs + reg); in xlgmac_config_queue_mapping()
1634 u32 regval; in xlgmac_config_tx_fifo_size() local
1641 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR)); in xlgmac_config_tx_fifo_size()
1642 regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_TQOMR_TQS_POS, in xlgmac_config_tx_fifo_size()
1644 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR)); in xlgmac_config_tx_fifo_size()
1656 u32 regval; in xlgmac_config_rx_fifo_size() local
1663 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); in xlgmac_config_rx_fifo_size()
1664 regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQOMR_RQS_POS, in xlgmac_config_rx_fifo_size()
1666 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); in xlgmac_config_rx_fifo_size()
1677 u32 regval; in xlgmac_config_flow_control_threshold() local
1680 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQFCR)); in xlgmac_config_flow_control_threshold()
1682 regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQFCR_RFA_POS, in xlgmac_config_flow_control_threshold()
1685 regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQFCR_RFD_POS, in xlgmac_config_flow_control_threshold()
1687 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQFCR)); in xlgmac_config_flow_control_threshold()
1695 u32 regval; in xlgmac_config_tx_threshold() local
1698 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR)); in xlgmac_config_tx_threshold()
1699 regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_TQOMR_TTC_POS, in xlgmac_config_tx_threshold()
1701 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR)); in xlgmac_config_tx_threshold()
1711 u32 regval; in xlgmac_config_rsf_mode() local
1714 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); in xlgmac_config_rsf_mode()
1715 regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_RQOMR_RSF_POS, in xlgmac_config_rsf_mode()
1717 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_RQOMR)); in xlgmac_config_rsf_mode()
1727 u32 regval; in xlgmac_config_tsf_mode() local
1730 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR)); in xlgmac_config_tsf_mode()
1731 regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_TQOMR_TSF_POS, in xlgmac_config_tsf_mode()
1733 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR)); in xlgmac_config_tsf_mode()
1743 u32 regval; in xlgmac_config_osp_mode() local
1750 regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_TCR)); in xlgmac_config_osp_mode()
1751 regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_TCR_OSP_POS, in xlgmac_config_osp_mode()
1754 writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_TCR)); in xlgmac_config_osp_mode()
1764 u32 regval; in xlgmac_config_pblx8() local
1768 regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_CR)); in xlgmac_config_pblx8()
1769 regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_CR_PBLX8_POS, in xlgmac_config_pblx8()
1772 writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_CR)); in xlgmac_config_pblx8()
1780 u32 regval; in xlgmac_get_tx_pbl_val() local
1782 regval = readl(XLGMAC_DMA_REG(pdata->channel_head, DMA_CH_TCR)); in xlgmac_get_tx_pbl_val()
1783 regval = XLGMAC_GET_REG_BITS(regval, DMA_CH_TCR_PBL_POS, in xlgmac_get_tx_pbl_val()
1785 return regval; in xlgmac_get_tx_pbl_val()
1792 u32 regval; in xlgmac_config_tx_pbl_val() local
1799 regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_TCR)); in xlgmac_config_tx_pbl_val()
1800 regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_TCR_PBL_POS, in xlgmac_config_tx_pbl_val()
1803 writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_TCR)); in xlgmac_config_tx_pbl_val()
1811 u32 regval; in xlgmac_get_rx_pbl_val() local
1813 regval = readl(XLGMAC_DMA_REG(pdata->channel_head, DMA_CH_RCR)); in xlgmac_get_rx_pbl_val()
1814 regval = XLGMAC_GET_REG_BITS(regval, DMA_CH_RCR_PBL_POS, in xlgmac_get_rx_pbl_val()
1816 return regval; in xlgmac_get_rx_pbl_val()
1823 u32 regval; in xlgmac_config_rx_pbl_val() local
1830 regval = readl(XLGMAC_DMA_REG(channel, DMA_CH_RCR)); in xlgmac_config_rx_pbl_val()
1831 regval = XLGMAC_SET_REG_BITS(regval, DMA_CH_RCR_PBL_POS, in xlgmac_config_rx_pbl_val()
1834 writel(regval, XLGMAC_DMA_REG(channel, DMA_CH_RCR)); in xlgmac_config_rx_pbl_val()
2127 u32 regval; in xlgmac_read_mmc_stats() local
2130 regval = readl(pdata->mac_regs + MMC_CR); in xlgmac_read_mmc_stats()
2131 regval = XLGMAC_SET_REG_BITS(regval, MMC_CR_MCF_POS, in xlgmac_read_mmc_stats()
2133 writel(regval, pdata->mac_regs + MMC_CR); in xlgmac_read_mmc_stats()
2259 regval = readl(pdata->mac_regs + MMC_CR); in xlgmac_read_mmc_stats()
2260 regval = XLGMAC_SET_REG_BITS(regval, MMC_CR_MCF_POS, in xlgmac_read_mmc_stats()
2262 writel(regval, pdata->mac_regs + MMC_CR); in xlgmac_read_mmc_stats()
2267 u32 regval; in xlgmac_config_mmc() local
2269 regval = readl(pdata->mac_regs + MMC_CR); in xlgmac_config_mmc()
2271 regval = XLGMAC_SET_REG_BITS(regval, MMC_CR_ROR_POS, in xlgmac_config_mmc()
2274 regval = XLGMAC_SET_REG_BITS(regval, MMC_CR_CR_POS, in xlgmac_config_mmc()
2276 writel(regval, pdata->mac_regs + MMC_CR); in xlgmac_config_mmc()
2284 u32 regval; in xlgmac_write_rss_reg() local
2288 regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_RSSAR), in xlgmac_write_rss_reg()
2290 if (regval) { in xlgmac_write_rss_reg()
2297 regval = readl(pdata->mac_regs + MAC_RSSAR); in xlgmac_write_rss_reg()
2298 regval = XLGMAC_SET_REG_BITS(regval, MAC_RSSAR_RSSIA_POS, in xlgmac_write_rss_reg()
2300 regval = XLGMAC_SET_REG_BITS(regval, MAC_RSSAR_ADDRT_POS, in xlgmac_write_rss_reg()
2302 regval = XLGMAC_SET_REG_BITS(regval, MAC_RSSAR_CT_POS, in xlgmac_write_rss_reg()
2304 regval = XLGMAC_SET_REG_BITS(regval, MAC_RSSAR_OB_POS, in xlgmac_write_rss_reg()
2306 writel(regval, pdata->mac_regs + MAC_RSSAR); in xlgmac_write_rss_reg()
2310 regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_RSSAR), in xlgmac_write_rss_reg()
2313 if (!regval) in xlgmac_write_rss_reg()
2386 u32 regval; in xlgmac_enable_rss() local
2406 regval = readl(pdata->mac_regs + MAC_RSSCR); in xlgmac_enable_rss()
2407 regval = XLGMAC_SET_REG_BITS(regval, MAC_RSSCR_RSSE_POS, in xlgmac_enable_rss()
2409 writel(regval, pdata->mac_regs + MAC_RSSCR); in xlgmac_enable_rss()
2416 u32 regval; in xlgmac_disable_rss() local
2421 regval = readl(pdata->mac_regs + MAC_RSSCR); in xlgmac_disable_rss()
2422 regval = XLGMAC_SET_REG_BITS(regval, MAC_RSSCR_RSSE_POS, in xlgmac_disable_rss()
2424 writel(regval, pdata->mac_regs + MAC_RSSCR); in xlgmac_disable_rss()
2530 u32 regval; in xlgmac_enable_mac_interrupts() local
2539 regval = readl(pdata->mac_regs + MMC_RIER); in xlgmac_enable_mac_interrupts()
2540 regval = XLGMAC_SET_REG_BITS(regval, MMC_RIER_ALL_INTERRUPTS_POS, in xlgmac_enable_mac_interrupts()
2542 writel(regval, pdata->mac_regs + MMC_RIER); in xlgmac_enable_mac_interrupts()
2543 regval = readl(pdata->mac_regs + MMC_TIER); in xlgmac_enable_mac_interrupts()
2544 regval = XLGMAC_SET_REG_BITS(regval, MMC_TIER_ALL_INTERRUPTS_POS, in xlgmac_enable_mac_interrupts()
2546 writel(regval, pdata->mac_regs + MMC_TIER); in xlgmac_enable_mac_interrupts()
2551 u32 regval; in xlgmac_set_xlgmii_25000_speed() local
2553 regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_TCR), in xlgmac_set_xlgmii_25000_speed()
2555 if (regval == 0x1) in xlgmac_set_xlgmii_25000_speed()
2558 regval = readl(pdata->mac_regs + MAC_TCR); in xlgmac_set_xlgmii_25000_speed()
2559 regval = XLGMAC_SET_REG_BITS(regval, MAC_TCR_SS_POS, in xlgmac_set_xlgmii_25000_speed()
2561 writel(regval, pdata->mac_regs + MAC_TCR); in xlgmac_set_xlgmii_25000_speed()
2568 u32 regval; in xlgmac_set_xlgmii_40000_speed() local
2570 regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_TCR), in xlgmac_set_xlgmii_40000_speed()
2572 if (regval == 0) in xlgmac_set_xlgmii_40000_speed()
2575 regval = readl(pdata->mac_regs + MAC_TCR); in xlgmac_set_xlgmii_40000_speed()
2576 regval = XLGMAC_SET_REG_BITS(regval, MAC_TCR_SS_POS, in xlgmac_set_xlgmii_40000_speed()
2578 writel(regval, pdata->mac_regs + MAC_TCR); in xlgmac_set_xlgmii_40000_speed()
2585 u32 regval; in xlgmac_set_xlgmii_50000_speed() local
2587 regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_TCR), in xlgmac_set_xlgmii_50000_speed()
2589 if (regval == 0x2) in xlgmac_set_xlgmii_50000_speed()
2592 regval = readl(pdata->mac_regs + MAC_TCR); in xlgmac_set_xlgmii_50000_speed()
2593 regval = XLGMAC_SET_REG_BITS(regval, MAC_TCR_SS_POS, in xlgmac_set_xlgmii_50000_speed()
2595 writel(regval, pdata->mac_regs + MAC_TCR); in xlgmac_set_xlgmii_50000_speed()
2602 u32 regval; in xlgmac_set_xlgmii_100000_speed() local
2604 regval = XLGMAC_GET_REG_BITS(readl(pdata->mac_regs + MAC_TCR), in xlgmac_set_xlgmii_100000_speed()
2606 if (regval == 0x3) in xlgmac_set_xlgmii_100000_speed()
2609 regval = readl(pdata->mac_regs + MAC_TCR); in xlgmac_set_xlgmii_100000_speed()
2610 regval = XLGMAC_SET_REG_BITS(regval, MAC_TCR_SS_POS, in xlgmac_set_xlgmii_100000_speed()
2612 writel(regval, pdata->mac_regs + MAC_TCR); in xlgmac_set_xlgmii_100000_speed()
2946 u32 regval; in xlgmac_flush_tx_queues() local
2949 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR)); in xlgmac_flush_tx_queues()
2950 regval = XLGMAC_SET_REG_BITS(regval, MTL_Q_TQOMR_FTQ_POS, in xlgmac_flush_tx_queues()
2952 writel(regval, XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR)); in xlgmac_flush_tx_queues()
2958 regval = readl(XLGMAC_MTL_REG(pdata, i, MTL_Q_TQOMR)); in xlgmac_flush_tx_queues()
2959 regval = XLGMAC_GET_REG_BITS(regval, MTL_Q_TQOMR_FTQ_POS, in xlgmac_flush_tx_queues()
2961 while (--count && regval) in xlgmac_flush_tx_queues()
2973 u32 regval; in xlgmac_config_dma_bus() local
2975 regval = readl(pdata->mac_regs + DMA_SBMR); in xlgmac_config_dma_bus()
2977 regval = XLGMAC_SET_REG_BITS(regval, DMA_SBMR_EAME_POS, in xlgmac_config_dma_bus()
2980 regval = XLGMAC_SET_REG_BITS(regval, DMA_SBMR_UNDEF_POS, in xlgmac_config_dma_bus()
2982 regval = XLGMAC_SET_REG_BITS(regval, DMA_SBMR_BLEN_256_POS, in xlgmac_config_dma_bus()
2984 writel(regval, pdata->mac_regs + DMA_SBMR); in xlgmac_config_dma_bus()
3044 u32 regval; in xlgmac_hw_exit() local
3047 regval = readl(pdata->mac_regs + DMA_MR); in xlgmac_hw_exit()
3048 regval = XLGMAC_SET_REG_BITS(regval, DMA_MR_SWR_POS, in xlgmac_hw_exit()
3050 writel(regval, pdata->mac_regs + DMA_MR); in xlgmac_hw_exit()