Lines Matching refs:phy_write_mmd
249 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_LTC_LOAD_CTRL, in _nxp_c45_ptp_gettimex64()
281 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_LTC_WR_NSEC_0, in _nxp_c45_ptp_settime64()
283 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_LTC_WR_NSEC_1, in _nxp_c45_ptp_settime64()
285 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_LTC_WR_SEC_0, in _nxp_c45_ptp_settime64()
287 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_LTC_WR_SEC_1, in _nxp_c45_ptp_settime64()
289 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_LTC_LOAD_CTRL, in _nxp_c45_ptp_settime64()
320 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_RATE_ADJ_SUBNS_0, in nxp_c45_ptp_adjfine()
327 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_RATE_ADJ_SUBNS_1, in nxp_c45_ptp_adjfine()
379 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_EXT_TRG_TS_CTRL, in nxp_c45_get_extts()
390 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_EGR_RING_CTRL, in nxp_c45_get_hwtxts()
504 phy_write_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_gpio_config()
763 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_EVENT_MSG_FILT, in nxp_c45_hwtstamp()
769 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_EVENT_MSG_FILT, in nxp_c45_hwtstamp()
870 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONTROL, in nxp_c45_config_enable()
875 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_CONTROL, in nxp_c45_config_enable()
877 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONTROL, in nxp_c45_config_enable()
879 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_INFRA_CONTROL, in nxp_c45_config_enable()
910 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_IRQ_ACK, in nxp_c45_handle_interrupt()
935 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONTROL, in nxp_c45_soft_reset()
948 return phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_CABLE_TEST, in nxp_c45_cable_test_start()
996 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, PMAPMD_B100T1_PMAPMD_CTL, in nxp_c45_setup_master_slave()
1001 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, PMAPMD_B100T1_PMAPMD_CTL, in nxp_c45_setup_master_slave()
1117 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID, in nxp_c45_set_delays()
1127 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID, in nxp_c45_set_delays()
1188 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, in nxp_c45_set_phy_mode()
1199 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, in nxp_c45_set_phy_mode()
1212 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, in nxp_c45_set_phy_mode()
1220 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, in nxp_c45_set_phy_mode()
1228 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, in nxp_c45_set_phy_mode()
1236 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, in nxp_c45_set_phy_mode()
1261 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 1); in nxp_c45_config_init()
1262 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 2); in nxp_c45_config_init()
1284 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PTP_CLK_PERIOD, in nxp_c45_config_init()
1288 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_RX_TS_INSRT_CTRL, in nxp_c45_config_init()