Lines Matching defs:ath5k_hw
1258 struct ath5k_hw { struct
1259 struct ath_common common;
1261 struct pci_dev *pdev;
1262 struct device *dev; /* for dma mapping */
1263 int irq;
1264 u16 devid;
1265 void __iomem *iobase; /* address of the device */
1266 struct mutex lock; /* dev-level lock */
1267 struct ieee80211_hw *hw; /* IEEE 802.11 common */
1268 struct ieee80211_supported_band sbands[NUM_NL80211_BANDS];
1269 struct ieee80211_channel channels[ATH_CHAN_MAX];
1270 struct ieee80211_rate rates[NUM_NL80211_BANDS][AR5K_MAX_RATES];
1271 s8 rate_idx[NUM_NL80211_BANDS][AR5K_MAX_RATES];
1272 enum nl80211_iftype opmode;
1275 struct ath5k_dbg_info debug; /* debug info */
1278 struct ath5k_buf *bufptr; /* allocated buffer ptr */
1279 struct ath5k_desc *desc; /* TX/RX descriptors */
1280 dma_addr_t desc_daddr; /* DMA (physical) address */
1281 size_t desc_len; /* size of TX/RX descriptors */
1289 unsigned int filter_flags; /* HW flags, AR5K_RX_FILTER_* */
1290 unsigned int fif_filter_flags; /* Current FIF_* filter flags */
1291 struct ieee80211_channel *curchan; /* current h/w channel */
1293 u16 nvifs;
1295 enum ath5k_int imask; /* interrupt mask copy */
1297 spinlock_t irqlock;
1298 bool rx_pending; /* rx tasklet pending */
1299 bool tx_pending; /* tx tasklet pending */
1301 u8 bssidmask[ETH_ALEN];
1303 unsigned int led_pin, /* GPIO pin for driving LED */
1304 led_on; /* pin setting for LED on */
1306 struct work_struct reset_work; /* deferred chip reset */
1307 struct work_struct calib_work; /* deferred phy calibration */
1309 struct list_head rxbuf; /* receive buffer */
1310 spinlock_t rxbuflock;
1311 u32 *rxlink; /* link ptr in last RX desc */
1312 struct tasklet_struct rxtq; /* rx intr tasklet */
1313 struct ath5k_led rx_led; /* rx led */
1315 struct list_head txbuf; /* transmit buffer */
1316 spinlock_t txbuflock;
1317 unsigned int txbuf_len; /* buf count in txbuf list */
1318 struct ath5k_txq txqs[AR5K_NUM_TX_QUEUES]; /* tx queues */
1319 struct tasklet_struct txtq; /* tx intr tasklet */
1320 struct ath5k_led tx_led; /* tx led */
1322 struct ath5k_rfkill rf_kill;
1324 spinlock_t block; /* protects beacon */
1325 struct tasklet_struct beacontq; /* beacon intr tasklet */
1326 struct list_head bcbuf; /* beacon buffer */
1327 struct ieee80211_vif *bslot[ATH_BCBUF];
1328 u16 num_ap_vifs;
1329 u16 num_adhoc_vifs;
1330 u16 num_mesh_vifs;
1331 unsigned int bhalq, /* SW q for outgoing beacons */
1332 bmisscount, /* missed beacon transmits */
1333 bintval, /* beacon interval in TU */
1334 bsent;
1335 unsigned int nexttbtt; /* next beacon time in TU */
1336 struct ath5k_txq *cabq; /* content after beacon */
1338 bool assoc; /* associate state */
1339 bool enable_beacon; /* true if beacons are on */
1341 struct ath5k_statistics stats;
1343 struct ath5k_ani_state ani_state;
1344 struct tasklet_struct ani_tasklet; /* ANI calibration */
1346 struct delayed_work tx_complete_work;
1348 struct survey_info survey; /* collected survey info */
1350 enum ath5k_int ah_imr;
1352 struct ieee80211_channel *ah_current_channel;
1353 bool ah_iq_cal_needed;
1354 bool ah_single_chip;
1356 enum ath5k_version ah_version;
1357 enum ath5k_radio ah_radio;
1358 u32 ah_mac_srev;
1359 u16 ah_mac_version;
1360 u16 ah_phy_revision;
1361 u16 ah_radio_5ghz_revision;
1362 u16 ah_radio_2ghz_revision;
1367 u8 ah_retry_long;
1368 u8 ah_retry_short;
1370 bool ah_use_32khz_clock;
1372 u8 ah_coverage_class;
1373 bool ah_ack_bitrate_high;
1374 u8 ah_bwmode;
1375 bool ah_short_slot;
1378 u32 ah_ant_ctl[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
1379 u8 ah_ant_mode;
1380 u8 ah_tx_ant;
1381 u8 ah_def_ant;
1383 struct ath5k_capabilities ah_capabilities;
1385 struct ath5k_txq_info ah_txq[AR5K_NUM_TX_QUEUES];
1386 u32 ah_txq_status;
1387 u32 ah_txq_imr_txok;
1388 u32 ah_txq_imr_txerr;
1389 u32 ah_txq_imr_txurn;
1390 u32 ah_txq_imr_txdesc;
1391 u32 ah_txq_imr_txeol;
1392 u32 ah_txq_imr_cbrorn;
1393 u32 ah_txq_imr_cbrurn;
1394 u32 ah_txq_imr_qtrig;
1395 u32 ah_txq_imr_nofrm;
1397 u32 ah_txq_isr_txok_all;
1399 u32 *ah_rf_banks;
1400 size_t ah_rf_banks_size;
1401 size_t ah_rf_regs_count;
1402 struct ath5k_gain ah_gain;
1403 u8 ah_offset[AR5K_MAX_RF_BANKS];
1406 struct {
1449 int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *, argument
1453 int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *, argument
1455 int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *, argument