Lines Matching refs:CSR_BASE
27 #define CSR_BASE (0x000) macro
29 #define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */
30 #define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
31 #define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */
32 #define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */
33 #define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/
34 #define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */
35 #define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
36 #define CSR_GP_CNTRL (CSR_BASE+0x024)
37 #define CSR_FUNC_SCRATCH (CSR_BASE+0x02c) /* Scratch register - used for FW dbg */
40 #define CSR_INT_PERIODIC_REG (CSR_BASE+0x005)
50 #define CSR_HW_REV (CSR_BASE+0x028)
61 #define CSR_HW_RF_ID (CSR_BASE+0x09c)
69 #define CSR_EEPROM_REG (CSR_BASE+0x02c)
70 #define CSR_EEPROM_GP (CSR_BASE+0x030)
71 #define CSR_OTP_GP_REG (CSR_BASE+0x034)
73 #define CSR_GIO_REG (CSR_BASE+0x03C)
74 #define CSR_GP_UCODE_REG (CSR_BASE+0x048)
75 #define CSR_GP_DRIVER_REG (CSR_BASE+0x050)
81 #define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054)
82 #define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058)
83 #define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c)
84 #define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060)
86 #define CSR_MBOX_SET_REG (CSR_BASE + 0x88)
88 #define CSR_LED_REG (CSR_BASE+0x094)
89 #define CSR_DRAM_INT_TBL_REG (CSR_BASE+0x0A0)
90 #define CSR_MAC_SHADOW_REG_CTRL (CSR_BASE + 0x0A8) /* 6000 and up */
92 #define CSR_MAC_SHADOW_REG_CTL2 (CSR_BASE + 0x0AC)
96 #define CSR_LTR_LONG_VAL_AD (CSR_BASE + 0x0D4)
106 #define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100)
108 #define CSR_IPC_SLEEP_CONTROL (CSR_BASE + 0x114)
115 #define CSR_DOORBELL_VECTOR (CSR_BASE + 0x130)
118 #define CSR_HOST_CHICKEN (CSR_BASE + 0x204)
122 #define CSR_ANA_PLL_CFG (CSR_BASE+0x20c)
127 #define CSR_MONITOR_CFG_REG (CSR_BASE+0x214)
128 #define CSR_MONITOR_STATUS_REG (CSR_BASE+0x228)
139 #define CSR_HW_REV_WA_REG (CSR_BASE+0x22C)
141 #define CSR_DBG_HPET_MEM_REG (CSR_BASE+0x240)
142 #define CSR_DBG_LINK_PWR_MGMT_REG (CSR_BASE+0x250)
475 #define HEEP_CTRL_WRD_PCIEX_CTRL_REG (CSR_BASE+0x0ec)
476 #define HEEP_CTRL_WRD_PCIEX_DATA_REG (CSR_BASE+0x0f4)