Lines Matching refs:CFG
15 u32 val = mt76_rr(dev, MT_VEND_ADDR(CFG, MT_USB_U3DMA_CFG)); in mt76x2u_init_dma()
25 mt76_wr(dev, MT_VEND_ADDR(CFG, MT_USB_U3DMA_CFG), val); in mt76x2u_init_dma()
30 mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), BIT(0) | BIT(16)); in mt76x2u_power_on_rf_patch()
33 mt76_clear(dev, MT_VEND_ADDR(CFG, 0x1c), 0xff); in mt76x2u_power_on_rf_patch()
34 mt76_set(dev, MT_VEND_ADDR(CFG, 0x1c), 0x30); in mt76x2u_power_on_rf_patch()
36 mt76_wr(dev, MT_VEND_ADDR(CFG, 0x14), 0x484f); in mt76x2u_power_on_rf_patch()
39 mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), BIT(17)); in mt76x2u_power_on_rf_patch()
42 mt76_clear(dev, MT_VEND_ADDR(CFG, 0x130), BIT(16)); in mt76x2u_power_on_rf_patch()
45 mt76_set(dev, MT_VEND_ADDR(CFG, 0x14c), BIT(19) | BIT(20)); in mt76x2u_power_on_rf_patch()
54 mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), BIT(0) << shift); in mt76x2u_power_on_rf()
58 mt76_set(dev, MT_VEND_ADDR(CFG, 0x130), val); in mt76x2u_power_on_rf()
62 mt76_clear(dev, MT_VEND_ADDR(CFG, 0x130), BIT(2) << shift); in mt76x2u_power_on_rf()
75 mt76_set(dev, MT_VEND_ADDR(CFG, 0x148), in mt76x2u_power_on()
82 mt76_poll(dev, MT_VEND_ADDR(CFG, 0x148), val, val, 1000); in mt76x2u_power_on()
84 mt76_clear(dev, MT_VEND_ADDR(CFG, 0x148), 0x7f << 16); in mt76x2u_power_on()
87 mt76_clear(dev, MT_VEND_ADDR(CFG, 0x148), 0xf << 24); in mt76x2u_power_on()
90 mt76_set(dev, MT_VEND_ADDR(CFG, 0x148), 0xf << 24); in mt76x2u_power_on()
91 mt76_clear(dev, MT_VEND_ADDR(CFG, 0x148), 0xfff); in mt76x2u_power_on()
94 mt76_clear(dev, MT_VEND_ADDR(CFG, 0x1204), BIT(3)); in mt76x2u_power_on()
97 mt76_set(dev, MT_VEND_ADDR(CFG, 0x80), BIT(0)); in mt76x2u_power_on()
100 mt76_clear(dev, MT_VEND_ADDR(CFG, 0x64), BIT(18)); in mt76x2u_power_on()