Lines Matching refs:priv
481 static int rtl8192eu_identify_chip(struct rtl8xxxu_priv *priv) in rtl8192eu_identify_chip() argument
483 struct device *dev = &priv->udev->dev; in rtl8192eu_identify_chip()
487 sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG); in rtl8192eu_identify_chip()
488 priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK); in rtl8192eu_identify_chip()
495 bonding = rtl8xxxu_read32(priv, REG_HPON_FSM); in rtl8192eu_identify_chip()
498 strscpy(priv->chip_name, "8191EU", sizeof(priv->chip_name)); in rtl8192eu_identify_chip()
499 priv->tx_paths = 1; in rtl8192eu_identify_chip()
500 priv->rtl_chip = RTL8191E; in rtl8192eu_identify_chip()
502 strscpy(priv->chip_name, "8192EU", sizeof(priv->chip_name)); in rtl8192eu_identify_chip()
503 priv->tx_paths = 2; in rtl8192eu_identify_chip()
504 priv->rtl_chip = RTL8192E; in rtl8192eu_identify_chip()
506 priv->rf_paths = 2; in rtl8192eu_identify_chip()
507 priv->rx_paths = 2; in rtl8192eu_identify_chip()
508 priv->has_wifi = 1; in rtl8192eu_identify_chip()
511 rtl8xxxu_identify_vendor_2bits(priv, vendor); in rtl8192eu_identify_chip()
513 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS); in rtl8192eu_identify_chip()
514 priv->rom_rev = u32_get_bits(val32, GPIO_RF_RL_ID); in rtl8192eu_identify_chip()
516 rtl8xxxu_config_endpoints_sie(priv); in rtl8192eu_identify_chip()
521 if (!priv->ep_tx_count) in rtl8192eu_identify_chip()
522 ret = rtl8xxxu_config_endpoints_no_sie(priv); in rtl8192eu_identify_chip()
529 rtl8192e_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) in rtl8192e_set_tx_power() argument
538 cck = priv->cck_tx_power_index_A[group]; in rtl8192e_set_tx_power()
540 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); in rtl8192e_set_tx_power()
543 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); in rtl8192e_set_tx_power()
545 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); in rtl8192e_set_tx_power()
548 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); in rtl8192e_set_tx_power()
550 ofdmbase = priv->ht40_1s_tx_power_index_A[group]; in rtl8192e_set_tx_power()
551 ofdmbase += priv->ofdm_tx_power_diff[tx_idx].a; in rtl8192e_set_tx_power()
554 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm); in rtl8192e_set_tx_power()
555 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm); in rtl8192e_set_tx_power()
557 mcsbase = priv->ht40_1s_tx_power_index_A[group]; in rtl8192e_set_tx_power()
559 mcsbase += priv->ht40_tx_power_diff[tx_idx++].a; in rtl8192e_set_tx_power()
561 mcsbase += priv->ht20_tx_power_diff[tx_idx++].a; in rtl8192e_set_tx_power()
564 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs); in rtl8192e_set_tx_power()
565 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs); in rtl8192e_set_tx_power()
566 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs); in rtl8192e_set_tx_power()
567 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs); in rtl8192e_set_tx_power()
569 if (priv->tx_paths > 1) { in rtl8192e_set_tx_power()
570 cck = priv->cck_tx_power_index_B[group]; in rtl8192e_set_tx_power()
572 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32); in rtl8192e_set_tx_power()
575 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32); in rtl8192e_set_tx_power()
577 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); in rtl8192e_set_tx_power()
580 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); in rtl8192e_set_tx_power()
582 ofdmbase = priv->ht40_1s_tx_power_index_B[group]; in rtl8192e_set_tx_power()
583 ofdmbase += priv->ofdm_tx_power_diff[tx_idx].b; in rtl8192e_set_tx_power()
587 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm); in rtl8192e_set_tx_power()
588 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm); in rtl8192e_set_tx_power()
590 mcsbase = priv->ht40_1s_tx_power_index_B[group]; in rtl8192e_set_tx_power()
592 mcsbase += priv->ht40_tx_power_diff[tx_idx++].b; in rtl8192e_set_tx_power()
594 mcsbase += priv->ht20_tx_power_diff[tx_idx++].b; in rtl8192e_set_tx_power()
597 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs); in rtl8192e_set_tx_power()
598 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs); in rtl8192e_set_tx_power()
599 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs); in rtl8192e_set_tx_power()
600 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs); in rtl8192e_set_tx_power()
604 static void rtl8192eu_log_next_device_info(struct rtl8xxxu_priv *priv, in rtl8192eu_log_next_device_info() argument
619 dev_warn(&priv->udev->dev, in rtl8192eu_log_next_device_info()
630 dev_info(&priv->udev->dev, "%s: %s\n", record_name, value); in rtl8192eu_log_next_device_info()
633 dev_info(&priv->udev->dev, "%s not available.\n", record_name); in rtl8192eu_log_next_device_info()
637 static int rtl8192eu_parse_efuse(struct rtl8xxxu_priv *priv) in rtl8192eu_parse_efuse() argument
639 struct rtl8192eu_efuse *efuse = &priv->efuse_wifi.efuse8192eu; in rtl8192eu_parse_efuse()
646 ether_addr_copy(priv->mac_addr, efuse->mac_addr); in rtl8192eu_parse_efuse()
648 memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base, in rtl8192eu_parse_efuse()
650 memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base, in rtl8192eu_parse_efuse()
653 memcpy(priv->ht40_1s_tx_power_index_A, in rtl8192eu_parse_efuse()
656 memcpy(priv->ht40_1s_tx_power_index_B, in rtl8192eu_parse_efuse()
660 priv->ht20_tx_power_diff[0].a = in rtl8192eu_parse_efuse()
662 priv->ht20_tx_power_diff[0].b = in rtl8192eu_parse_efuse()
665 priv->ht40_tx_power_diff[0].a = 0; in rtl8192eu_parse_efuse()
666 priv->ht40_tx_power_diff[0].b = 0; in rtl8192eu_parse_efuse()
669 priv->ofdm_tx_power_diff[i].a = in rtl8192eu_parse_efuse()
671 priv->ofdm_tx_power_diff[i].b = in rtl8192eu_parse_efuse()
674 priv->ht20_tx_power_diff[i].a = in rtl8192eu_parse_efuse()
676 priv->ht20_tx_power_diff[i].b = in rtl8192eu_parse_efuse()
679 priv->ht40_tx_power_diff[i].a = in rtl8192eu_parse_efuse()
681 priv->ht40_tx_power_diff[i].b = in rtl8192eu_parse_efuse()
685 priv->default_crystal_cap = priv->efuse_wifi.efuse8192eu.xtal_k & 0x3f; in rtl8192eu_parse_efuse()
703 rtl8192eu_log_next_device_info(priv, "Vendor", efuse->device_info, &record_offset); in rtl8192eu_parse_efuse()
704 rtl8192eu_log_next_device_info(priv, "Product", efuse->device_info, &record_offset); in rtl8192eu_parse_efuse()
705 rtl8192eu_log_next_device_info(priv, "Serial", efuse->device_info, &record_offset); in rtl8192eu_parse_efuse()
710 static int rtl8192eu_load_firmware(struct rtl8xxxu_priv *priv) in rtl8192eu_load_firmware() argument
717 ret = rtl8xxxu_load_firmware(priv, fw_name); in rtl8192eu_load_firmware()
722 static void rtl8192eu_init_phy_bb(struct rtl8xxxu_priv *priv) in rtl8192eu_init_phy_bb() argument
727 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); in rtl8192eu_init_phy_bb()
729 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); in rtl8192eu_init_phy_bb()
733 rtl8xxxu_write8(priv, REG_RF_CTRL, val8); in rtl8192eu_init_phy_bb()
735 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); in rtl8192eu_init_phy_bb()
738 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); in rtl8192eu_init_phy_bb()
740 rtl8xxxu_write8(priv, REG_RF_CTRL, val8); in rtl8192eu_init_phy_bb()
741 rtl8xxxu_init_phy_regs(priv, rtl8192eu_phy_init_table); in rtl8192eu_init_phy_bb()
743 if (priv->hi_pa) in rtl8192eu_init_phy_bb()
744 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8192eu_highpa_table); in rtl8192eu_init_phy_bb()
746 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8192eu_std_table); in rtl8192eu_init_phy_bb()
749 static int rtl8192eu_init_phy_rf(struct rtl8xxxu_priv *priv) in rtl8192eu_init_phy_rf() argument
753 ret = rtl8xxxu_init_phy_rf(priv, rtl8192eu_radioa_init_table, RF_A); in rtl8192eu_init_phy_rf()
757 ret = rtl8xxxu_init_phy_rf(priv, rtl8192eu_radiob_init_table, RF_B); in rtl8192eu_init_phy_rf()
763 static int rtl8192eu_iqk_path_a(struct rtl8xxxu_priv *priv) in rtl8192eu_iqk_path_a() argument
772 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_iqk_path_a()
773 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00180); in rtl8192eu_iqk_path_a()
775 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0); in rtl8192eu_iqk_path_a()
776 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000); in rtl8192eu_iqk_path_a()
777 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); in rtl8192eu_iqk_path_a()
778 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0x07f77); in rtl8192eu_iqk_path_a()
780 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_iqk_path_a()
783 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); in rtl8192eu_iqk_path_a()
784 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); in rtl8192eu_iqk_path_a()
785 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); in rtl8192eu_iqk_path_a()
786 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); in rtl8192eu_iqk_path_a()
788 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140303); in rtl8192eu_iqk_path_a()
789 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x68160000); in rtl8192eu_iqk_path_a()
792 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911); in rtl8192eu_iqk_path_a()
795 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); in rtl8192eu_iqk_path_a()
796 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); in rtl8192eu_iqk_path_a()
801 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); in rtl8192eu_iqk_path_a()
802 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); in rtl8192eu_iqk_path_a()
803 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); in rtl8192eu_iqk_path_a()
813 static int rtl8192eu_rx_iqk_path_a(struct rtl8xxxu_priv *priv) in rtl8192eu_rx_iqk_path_a() argument
819 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00); in rtl8192eu_rx_iqk_path_a()
822 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0); in rtl8192eu_rx_iqk_path_a()
823 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); in rtl8192eu_rx_iqk_path_a()
824 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); in rtl8192eu_rx_iqk_path_a()
825 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf1173); in rtl8192eu_rx_iqk_path_a()
827 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0); in rtl8192eu_rx_iqk_path_a()
828 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000); in rtl8192eu_rx_iqk_path_a()
829 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f); in rtl8192eu_rx_iqk_path_a()
830 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf1173); in rtl8192eu_rx_iqk_path_a()
833 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00980); in rtl8192eu_rx_iqk_path_a()
834 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, 0x511e0); in rtl8192eu_rx_iqk_path_a()
837 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_rx_iqk_path_a()
840 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); in rtl8192eu_rx_iqk_path_a()
841 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8192eu_rx_iqk_path_a()
844 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); in rtl8192eu_rx_iqk_path_a()
845 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); in rtl8192eu_rx_iqk_path_a()
846 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); in rtl8192eu_rx_iqk_path_a()
847 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); in rtl8192eu_rx_iqk_path_a()
849 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x8216031f); in rtl8192eu_rx_iqk_path_a()
850 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x6816031f); in rtl8192eu_rx_iqk_path_a()
853 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); in rtl8192eu_rx_iqk_path_a()
856 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); in rtl8192eu_rx_iqk_path_a()
857 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); in rtl8192eu_rx_iqk_path_a()
862 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); in rtl8192eu_rx_iqk_path_a()
863 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); in rtl8192eu_rx_iqk_path_a()
864 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); in rtl8192eu_rx_iqk_path_a()
872 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_rx_iqk_path_a()
873 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x180); in rtl8192eu_rx_iqk_path_a()
879 rtl8xxxu_write32(priv, REG_TX_IQK, val32); in rtl8192eu_rx_iqk_path_a()
882 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_rx_iqk_path_a()
884 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0); in rtl8192eu_rx_iqk_path_a()
885 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); in rtl8192eu_rx_iqk_path_a()
886 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); in rtl8192eu_rx_iqk_path_a()
887 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ff2); in rtl8192eu_rx_iqk_path_a()
889 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0); in rtl8192eu_rx_iqk_path_a()
890 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000); in rtl8192eu_rx_iqk_path_a()
891 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f); in rtl8192eu_rx_iqk_path_a()
892 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf7ff2); in rtl8192eu_rx_iqk_path_a()
895 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00980); in rtl8192eu_rx_iqk_path_a()
896 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, 0x510e0); in rtl8192eu_rx_iqk_path_a()
899 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_rx_iqk_path_a()
902 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8192eu_rx_iqk_path_a()
905 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); in rtl8192eu_rx_iqk_path_a()
906 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c); in rtl8192eu_rx_iqk_path_a()
907 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); in rtl8192eu_rx_iqk_path_a()
908 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); in rtl8192eu_rx_iqk_path_a()
910 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821608ff); in rtl8192eu_rx_iqk_path_a()
911 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x281608ff); in rtl8192eu_rx_iqk_path_a()
914 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a891); in rtl8192eu_rx_iqk_path_a()
917 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); in rtl8192eu_rx_iqk_path_a()
918 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); in rtl8192eu_rx_iqk_path_a()
922 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); in rtl8192eu_rx_iqk_path_a()
923 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); in rtl8192eu_rx_iqk_path_a()
925 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_rx_iqk_path_a()
926 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x180); in rtl8192eu_rx_iqk_path_a()
933 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n", in rtl8192eu_rx_iqk_path_a()
940 static int rtl8192eu_iqk_path_b(struct rtl8xxxu_priv *priv) in rtl8192eu_iqk_path_b() argument
945 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_iqk_path_b()
946 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x00180); in rtl8192eu_iqk_path_b()
948 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0); in rtl8192eu_iqk_path_b()
949 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x20000); in rtl8192eu_iqk_path_b()
950 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f); in rtl8192eu_iqk_path_b()
951 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0x07f77); in rtl8192eu_iqk_path_b()
953 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_iqk_path_b()
956 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); in rtl8192eu_iqk_path_b()
957 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); in rtl8192eu_iqk_path_b()
958 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c); in rtl8192eu_iqk_path_b()
959 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); in rtl8192eu_iqk_path_b()
961 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140303); in rtl8192eu_iqk_path_b()
962 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x68160000); in rtl8192eu_iqk_path_b()
965 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911); in rtl8192eu_iqk_path_b()
968 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000); in rtl8192eu_iqk_path_b()
969 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); in rtl8192eu_iqk_path_b()
974 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); in rtl8192eu_iqk_path_b()
975 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); in rtl8192eu_iqk_path_b()
976 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); in rtl8192eu_iqk_path_b()
983 dev_warn(&priv->udev->dev, "%s: Path B IQK failed!\n", in rtl8192eu_iqk_path_b()
989 static int rtl8192eu_rx_iqk_path_b(struct rtl8xxxu_priv *priv) in rtl8192eu_rx_iqk_path_b() argument
995 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_rx_iqk_path_b()
998 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0); in rtl8192eu_rx_iqk_path_b()
999 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000); in rtl8192eu_rx_iqk_path_b()
1000 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f); in rtl8192eu_rx_iqk_path_b()
1001 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf1173); in rtl8192eu_rx_iqk_path_b()
1003 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0); in rtl8192eu_rx_iqk_path_b()
1004 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); in rtl8192eu_rx_iqk_path_b()
1005 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); in rtl8192eu_rx_iqk_path_b()
1006 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf1173); in rtl8192eu_rx_iqk_path_b()
1009 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x00980); in rtl8192eu_rx_iqk_path_b()
1010 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_56, 0x511e0); in rtl8192eu_rx_iqk_path_b()
1013 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_rx_iqk_path_b()
1016 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); in rtl8192eu_rx_iqk_path_b()
1017 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8192eu_rx_iqk_path_b()
1020 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); in rtl8192eu_rx_iqk_path_b()
1021 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); in rtl8192eu_rx_iqk_path_b()
1022 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c); in rtl8192eu_rx_iqk_path_b()
1023 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); in rtl8192eu_rx_iqk_path_b()
1025 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x8216031f); in rtl8192eu_rx_iqk_path_b()
1026 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x6816031f); in rtl8192eu_rx_iqk_path_b()
1029 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); in rtl8192eu_rx_iqk_path_b()
1032 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000); in rtl8192eu_rx_iqk_path_b()
1033 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); in rtl8192eu_rx_iqk_path_b()
1038 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); in rtl8192eu_rx_iqk_path_b()
1039 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); in rtl8192eu_rx_iqk_path_b()
1040 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); in rtl8192eu_rx_iqk_path_b()
1051 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_rx_iqk_path_b()
1052 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x180); in rtl8192eu_rx_iqk_path_b()
1058 rtl8xxxu_write32(priv, REG_TX_IQK, val32); in rtl8192eu_rx_iqk_path_b()
1061 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_rx_iqk_path_b()
1063 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0); in rtl8192eu_rx_iqk_path_b()
1064 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000); in rtl8192eu_rx_iqk_path_b()
1065 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f); in rtl8192eu_rx_iqk_path_b()
1066 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf7ff2); in rtl8192eu_rx_iqk_path_b()
1068 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0); in rtl8192eu_rx_iqk_path_b()
1069 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); in rtl8192eu_rx_iqk_path_b()
1070 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); in rtl8192eu_rx_iqk_path_b()
1071 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ff2); in rtl8192eu_rx_iqk_path_b()
1074 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x00980); in rtl8192eu_rx_iqk_path_b()
1075 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_56, 0x510e0); in rtl8192eu_rx_iqk_path_b()
1078 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_rx_iqk_path_b()
1081 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8192eu_rx_iqk_path_b()
1084 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); in rtl8192eu_rx_iqk_path_b()
1085 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); in rtl8192eu_rx_iqk_path_b()
1086 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); in rtl8192eu_rx_iqk_path_b()
1087 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x18008c1c); in rtl8192eu_rx_iqk_path_b()
1089 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821608ff); in rtl8192eu_rx_iqk_path_b()
1090 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x281608ff); in rtl8192eu_rx_iqk_path_b()
1093 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a891); in rtl8192eu_rx_iqk_path_b()
1096 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000); in rtl8192eu_rx_iqk_path_b()
1097 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); in rtl8192eu_rx_iqk_path_b()
1101 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); in rtl8192eu_rx_iqk_path_b()
1102 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); in rtl8192eu_rx_iqk_path_b()
1103 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); in rtl8192eu_rx_iqk_path_b()
1105 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_rx_iqk_path_b()
1106 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x180); in rtl8192eu_rx_iqk_path_b()
1113 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n", in rtl8192eu_rx_iqk_path_b()
1120 static void rtl8192eu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, in rtl8192eu_phy_iqcalibrate() argument
1123 struct device *dev = &priv->udev->dev; in rtl8192eu_phy_iqcalibrate()
1147 u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff; in rtl8192eu_phy_iqcalibrate()
1148 u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff; in rtl8192eu_phy_iqcalibrate()
1157 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, in rtl8192eu_phy_iqcalibrate()
1159 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); in rtl8192eu_phy_iqcalibrate()
1160 rtl8xxxu_save_regs(priv, iqk_bb_regs, in rtl8192eu_phy_iqcalibrate()
1161 priv->bb_backup, RTL8XXXU_BB_REGS); in rtl8192eu_phy_iqcalibrate()
1164 rtl8xxxu_path_adda_on(priv, adda_regs, true); in rtl8192eu_phy_iqcalibrate()
1167 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup); in rtl8192eu_phy_iqcalibrate()
1169 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING); in rtl8192eu_phy_iqcalibrate()
1171 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); in rtl8192eu_phy_iqcalibrate()
1173 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); in rtl8192eu_phy_iqcalibrate()
1174 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); in rtl8192eu_phy_iqcalibrate()
1175 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22208200); in rtl8192eu_phy_iqcalibrate()
1177 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL); in rtl8192eu_phy_iqcalibrate()
1179 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32); in rtl8192eu_phy_iqcalibrate()
1181 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE); in rtl8192eu_phy_iqcalibrate()
1183 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32); in rtl8192eu_phy_iqcalibrate()
1184 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); in rtl8192eu_phy_iqcalibrate()
1186 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32); in rtl8192eu_phy_iqcalibrate()
1188 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_phy_iqcalibrate()
1189 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); in rtl8192eu_phy_iqcalibrate()
1190 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8192eu_phy_iqcalibrate()
1193 path_a_ok = rtl8192eu_iqk_path_a(priv); in rtl8192eu_phy_iqcalibrate()
1195 val32 = rtl8xxxu_read32(priv, in rtl8192eu_phy_iqcalibrate()
1198 val32 = rtl8xxxu_read32(priv, in rtl8192eu_phy_iqcalibrate()
1210 path_a_ok = rtl8192eu_rx_iqk_path_a(priv); in rtl8192eu_phy_iqcalibrate()
1212 val32 = rtl8xxxu_read32(priv, in rtl8192eu_phy_iqcalibrate()
1215 val32 = rtl8xxxu_read32(priv, in rtl8192eu_phy_iqcalibrate()
1226 if (priv->rf_paths > 1) { in rtl8192eu_phy_iqcalibrate()
1228 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_phy_iqcalibrate()
1229 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000); in rtl8192eu_phy_iqcalibrate()
1230 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_phy_iqcalibrate()
1233 rtl8xxxu_path_adda_on(priv, adda_regs, false); in rtl8192eu_phy_iqcalibrate()
1235 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_phy_iqcalibrate()
1236 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); in rtl8192eu_phy_iqcalibrate()
1237 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8192eu_phy_iqcalibrate()
1240 path_b_ok = rtl8192eu_iqk_path_b(priv); in rtl8192eu_phy_iqcalibrate()
1242 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); in rtl8192eu_phy_iqcalibrate()
1244 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); in rtl8192eu_phy_iqcalibrate()
1254 path_b_ok = rtl8192eu_rx_iqk_path_b(priv); in rtl8192eu_phy_iqcalibrate()
1256 val32 = rtl8xxxu_read32(priv, in rtl8192eu_phy_iqcalibrate()
1259 val32 = rtl8xxxu_read32(priv, in rtl8192eu_phy_iqcalibrate()
1271 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_phy_iqcalibrate()
1275 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, in rtl8192eu_phy_iqcalibrate()
1279 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); in rtl8192eu_phy_iqcalibrate()
1282 rtl8xxxu_restore_regs(priv, iqk_bb_regs, in rtl8192eu_phy_iqcalibrate()
1283 priv->bb_backup, RTL8XXXU_BB_REGS); in rtl8192eu_phy_iqcalibrate()
1286 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); in rtl8192eu_phy_iqcalibrate()
1288 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50); in rtl8192eu_phy_iqcalibrate()
1289 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc); in rtl8192eu_phy_iqcalibrate()
1291 if (priv->rf_paths > 1) { in rtl8192eu_phy_iqcalibrate()
1292 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1); in rtl8192eu_phy_iqcalibrate()
1294 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1, in rtl8192eu_phy_iqcalibrate()
1296 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1, in rtl8192eu_phy_iqcalibrate()
1301 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); in rtl8192eu_phy_iqcalibrate()
1302 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); in rtl8192eu_phy_iqcalibrate()
1306 static void rtl8192eu_phy_iq_calibrate(struct rtl8xxxu_priv *priv) in rtl8192eu_phy_iq_calibrate() argument
1308 struct device *dev = &priv->udev->dev; in rtl8192eu_phy_iq_calibrate()
1323 rtl8192eu_phy_iqcalibrate(priv, result, i); in rtl8192eu_phy_iq_calibrate()
1326 simu = rtl8xxxu_gen2_simularity_compare(priv, in rtl8192eu_phy_iq_calibrate()
1335 simu = rtl8xxxu_gen2_simularity_compare(priv, in rtl8192eu_phy_iq_calibrate()
1342 simu = rtl8xxxu_gen2_simularity_compare(priv, in rtl8192eu_phy_iq_calibrate()
1362 priv->rege94 = reg_e94; in rtl8192eu_phy_iq_calibrate()
1364 priv->rege9c = reg_e9c; in rtl8192eu_phy_iq_calibrate()
1368 priv->regeb4 = reg_eb4; in rtl8192eu_phy_iq_calibrate()
1370 priv->regebc = reg_ebc; in rtl8192eu_phy_iq_calibrate()
1381 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100; in rtl8192eu_phy_iq_calibrate()
1382 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0; in rtl8192eu_phy_iq_calibrate()
1386 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, in rtl8192eu_phy_iq_calibrate()
1389 if (priv->rf_paths > 1) in rtl8192eu_phy_iq_calibrate()
1390 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result, in rtl8192eu_phy_iq_calibrate()
1393 rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg, in rtl8192eu_phy_iq_calibrate()
1394 priv->bb_recovery_backup, RTL8XXXU_BB_REGS); in rtl8192eu_phy_iq_calibrate()
1400 static void rtl8192e_crystal_afe_adjust(struct rtl8xxxu_priv *priv) in rtl8192e_crystal_afe_adjust() argument
1408 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL); in rtl8192e_crystal_afe_adjust()
1410 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8); in rtl8192e_crystal_afe_adjust()
1412 val32 = rtl8xxxu_read32(priv, REG_AFE_CTRL4); in rtl8192e_crystal_afe_adjust()
1414 rtl8xxxu_write32(priv, REG_AFE_CTRL4, val32); in rtl8192e_crystal_afe_adjust()
1420 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL); in rtl8192e_crystal_afe_adjust()
1422 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8); in rtl8192e_crystal_afe_adjust()
1427 val32 = rtl8xxxu_read32(priv, REG_AFE_CTRL4); in rtl8192e_crystal_afe_adjust()
1429 rtl8xxxu_write32(priv, REG_AFE_CTRL4, val32); in rtl8192e_crystal_afe_adjust()
1432 static void rtl8192e_disabled_to_emu(struct rtl8xxxu_priv *priv) in rtl8192e_disabled_to_emu() argument
1437 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); in rtl8192e_disabled_to_emu()
1439 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); in rtl8192e_disabled_to_emu()
1442 static int rtl8192e_emu_to_active(struct rtl8xxxu_priv *priv) in rtl8192e_emu_to_active() argument
1449 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); in rtl8192e_emu_to_active()
1451 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); in rtl8192e_emu_to_active()
1454 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); in rtl8192e_emu_to_active()
1456 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); in rtl8192e_emu_to_active()
1459 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); in rtl8192e_emu_to_active()
1461 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); in rtl8192e_emu_to_active()
1465 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8192e_emu_to_active()
1480 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2); in rtl8192e_emu_to_active()
1482 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8); in rtl8192e_emu_to_active()
1485 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8192e_emu_to_active()
1487 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8192e_emu_to_active()
1490 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8192e_emu_to_active()
1507 static int rtl8192eu_active_to_lps(struct rtl8xxxu_priv *priv) in rtl8192eu_active_to_lps() argument
1509 struct device *dev = &priv->udev->dev; in rtl8192eu_active_to_lps()
1515 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); in rtl8192eu_active_to_lps()
1523 val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD); in rtl8192eu_active_to_lps()
1537 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); in rtl8192eu_active_to_lps()
1539 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); in rtl8192eu_active_to_lps()
1544 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); in rtl8192eu_active_to_lps()
1546 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); in rtl8192eu_active_to_lps()
1549 val16 = rtl8xxxu_read16(priv, REG_CR); in rtl8192eu_active_to_lps()
1552 rtl8xxxu_write16(priv, REG_CR, val16); in rtl8192eu_active_to_lps()
1554 val16 = rtl8xxxu_read16(priv, REG_CR); in rtl8192eu_active_to_lps()
1556 rtl8xxxu_write16(priv, REG_CR, val16); in rtl8192eu_active_to_lps()
1558 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST); in rtl8192eu_active_to_lps()
1560 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8); in rtl8192eu_active_to_lps()
1566 static int rtl8192eu_active_to_emu(struct rtl8xxxu_priv *priv) in rtl8192eu_active_to_emu() argument
1572 val8 = rtl8xxxu_read8(priv, REG_RF_CTRL); in rtl8192eu_active_to_emu()
1574 rtl8xxxu_write8(priv, REG_RF_CTRL, val8); in rtl8192eu_active_to_emu()
1577 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2); in rtl8192eu_active_to_emu()
1579 rtl8xxxu_write8(priv, REG_LEDCFG2, val8); in rtl8192eu_active_to_emu()
1582 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); in rtl8192eu_active_to_emu()
1584 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); in rtl8192eu_active_to_emu()
1587 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); in rtl8192eu_active_to_emu()
1594 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n", in rtl8192eu_active_to_emu()
1604 static int rtl8192eu_emu_to_disabled(struct rtl8xxxu_priv *priv) in rtl8192eu_emu_to_disabled() argument
1609 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); in rtl8192eu_emu_to_disabled()
1612 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); in rtl8192eu_emu_to_disabled()
1617 static int rtl8192eu_power_on(struct rtl8xxxu_priv *priv) in rtl8192eu_power_on() argument
1623 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG); in rtl8192eu_power_on()
1625 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0xc3); in rtl8192eu_power_on()
1630 val32 = rtl8xxxu_read32(priv, REG_8192E_LDOV12_CTRL); in rtl8192eu_power_on()
1633 rtl8xxxu_write32(priv, REG_8192E_LDOV12_CTRL, val32); in rtl8192eu_power_on()
1634 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0x83); in rtl8192eu_power_on()
1640 rtl8192e_crystal_afe_adjust(priv); in rtl8192eu_power_on()
1641 rtl8192e_disabled_to_emu(priv); in rtl8192eu_power_on()
1643 ret = rtl8192e_emu_to_active(priv); in rtl8192eu_power_on()
1647 rtl8xxxu_write16(priv, REG_CR, 0x0000); in rtl8192eu_power_on()
1653 val16 = rtl8xxxu_read16(priv, REG_CR); in rtl8192eu_power_on()
1659 rtl8xxxu_write16(priv, REG_CR, val16); in rtl8192eu_power_on()
1665 static void rtl8192eu_power_off(struct rtl8xxxu_priv *priv) in rtl8192eu_power_off() argument
1670 rtl8xxxu_flush_fifo(priv); in rtl8192eu_power_off()
1672 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL); in rtl8192eu_power_off()
1674 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8); in rtl8192eu_power_off()
1677 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00); in rtl8192eu_power_off()
1679 rtl8192eu_active_to_lps(priv); in rtl8192eu_power_off()
1682 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) in rtl8192eu_power_off()
1683 rtl8xxxu_firmware_self_reset(priv); in rtl8192eu_power_off()
1686 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); in rtl8192eu_power_off()
1688 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); in rtl8192eu_power_off()
1691 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); in rtl8192eu_power_off()
1693 rtl8xxxu_reset_8051(priv); in rtl8192eu_power_off()
1695 rtl8192eu_active_to_emu(priv); in rtl8192eu_power_off()
1696 rtl8192eu_emu_to_disabled(priv); in rtl8192eu_power_off()
1699 static void rtl8192e_enable_rf(struct rtl8xxxu_priv *priv) in rtl8192e_enable_rf() argument
1704 val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA); in rtl8192e_enable_rf()
1706 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32); in rtl8192e_enable_rf()
1708 val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG); in rtl8192e_enable_rf()
1710 rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8); in rtl8192e_enable_rf()
1715 rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04); in rtl8192e_enable_rf()
1717 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA); in rtl8192e_enable_rf()
1719 rtl8xxxu_write32(priv, REG_PWR_DATA, val32); in rtl8192e_enable_rf()
1721 val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER); in rtl8192e_enable_rf()
1723 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32); in rtl8192e_enable_rf()
1725 rtl8xxxu_write8(priv, REG_RFE_CTRL_ANTA_SRC, 0x77); in rtl8192e_enable_rf()
1727 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); in rtl8192e_enable_rf()
1730 rtl8xxxu_write32(priv, REG_LEDCFG0, val32); in rtl8192e_enable_rf()
1735 val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1); in rtl8192e_enable_rf()
1737 rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8); in rtl8192e_enable_rf()
1742 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); in rtl8192e_enable_rf()
1745 static s8 rtl8192e_cck_rssi(struct rtl8xxxu_priv *priv, u8 cck_agc_rpt) in rtl8192e_cck_rssi() argument
1757 if (priv->cck_agc_report_type == 0) in rtl8192e_cck_rssi()
1770 struct rtl8xxxu_priv *priv = container_of(led_cdev, in rtl8192eu_led_brightness_set() local
1773 u8 ledcfg = rtl8xxxu_read8(priv, REG_LEDCFG1); in rtl8192eu_led_brightness_set()
1785 rtl8xxxu_write8(priv, REG_LEDCFG1, ledcfg); in rtl8192eu_led_brightness_set()