Lines Matching refs:priv
307 static int rtl8723bu_identify_chip(struct rtl8xxxu_priv *priv) in rtl8723bu_identify_chip() argument
309 struct device *dev = &priv->udev->dev; in rtl8723bu_identify_chip()
313 sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG); in rtl8723bu_identify_chip()
314 priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK); in rtl8723bu_identify_chip()
321 strscpy(priv->chip_name, "8723BU", sizeof(priv->chip_name)); in rtl8723bu_identify_chip()
322 priv->rtl_chip = RTL8723B; in rtl8723bu_identify_chip()
323 priv->rf_paths = 1; in rtl8723bu_identify_chip()
324 priv->rx_paths = 1; in rtl8723bu_identify_chip()
325 priv->tx_paths = 1; in rtl8723bu_identify_chip()
327 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL); in rtl8723bu_identify_chip()
329 priv->has_wifi = 1; in rtl8723bu_identify_chip()
331 priv->has_bluetooth = 1; in rtl8723bu_identify_chip()
333 priv->has_gps = 1; in rtl8723bu_identify_chip()
334 priv->is_multi_func = 1; in rtl8723bu_identify_chip()
337 rtl8xxxu_identify_vendor_2bits(priv, vendor); in rtl8723bu_identify_chip()
339 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS); in rtl8723bu_identify_chip()
340 priv->rom_rev = u32_get_bits(val32, GPIO_RF_RL_ID); in rtl8723bu_identify_chip()
342 rtl8xxxu_config_endpoints_sie(priv); in rtl8723bu_identify_chip()
347 if (!priv->ep_tx_count) in rtl8723bu_identify_chip()
348 ret = rtl8xxxu_config_endpoints_no_sie(priv); in rtl8723bu_identify_chip()
354 static void rtl8723bu_write_btreg(struct rtl8xxxu_priv *priv, u8 reg, u8 data) in rtl8723bu_write_btreg() argument
364 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper)); in rtl8723bu_write_btreg()
372 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper)); in rtl8723bu_write_btreg()
375 static void rtl8723bu_reset_8051(struct rtl8xxxu_priv *priv) in rtl8723bu_reset_8051() argument
380 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL); in rtl8723bu_reset_8051()
382 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8); in rtl8723bu_reset_8051()
384 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); in rtl8723bu_reset_8051()
386 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); in rtl8723bu_reset_8051()
388 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC); in rtl8723bu_reset_8051()
390 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); in rtl8723bu_reset_8051()
392 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL); in rtl8723bu_reset_8051()
394 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8); in rtl8723bu_reset_8051()
396 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); in rtl8723bu_reset_8051()
398 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); in rtl8723bu_reset_8051()
401 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); in rtl8723bu_reset_8051()
405 rtl8723b_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) in rtl8723b_set_tx_power() argument
414 cck = priv->cck_tx_power_index_B[group]; in rtl8723b_set_tx_power()
415 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); in rtl8723b_set_tx_power()
418 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); in rtl8723b_set_tx_power()
420 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); in rtl8723b_set_tx_power()
423 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); in rtl8723b_set_tx_power()
425 ofdmbase = priv->ht40_1s_tx_power_index_B[group]; in rtl8723b_set_tx_power()
426 ofdmbase += priv->ofdm_tx_power_diff[tx_idx].b; in rtl8723b_set_tx_power()
429 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm); in rtl8723b_set_tx_power()
430 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm); in rtl8723b_set_tx_power()
432 mcsbase = priv->ht40_1s_tx_power_index_B[group]; in rtl8723b_set_tx_power()
434 mcsbase += priv->ht40_tx_power_diff[tx_idx++].b; in rtl8723b_set_tx_power()
436 mcsbase += priv->ht20_tx_power_diff[tx_idx++].b; in rtl8723b_set_tx_power()
439 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs); in rtl8723b_set_tx_power()
440 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs); in rtl8723b_set_tx_power()
443 static int rtl8723bu_parse_efuse(struct rtl8xxxu_priv *priv) in rtl8723bu_parse_efuse() argument
445 struct rtl8723bu_efuse *efuse = &priv->efuse_wifi.efuse8723bu; in rtl8723bu_parse_efuse()
451 ether_addr_copy(priv->mac_addr, efuse->mac_addr); in rtl8723bu_parse_efuse()
453 memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base, in rtl8723bu_parse_efuse()
455 memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base, in rtl8723bu_parse_efuse()
458 memcpy(priv->ht40_1s_tx_power_index_A, in rtl8723bu_parse_efuse()
461 memcpy(priv->ht40_1s_tx_power_index_B, in rtl8723bu_parse_efuse()
465 priv->ofdm_tx_power_diff[0].a = in rtl8723bu_parse_efuse()
467 priv->ofdm_tx_power_diff[0].b = in rtl8723bu_parse_efuse()
470 priv->ht20_tx_power_diff[0].a = in rtl8723bu_parse_efuse()
472 priv->ht20_tx_power_diff[0].b = in rtl8723bu_parse_efuse()
475 priv->ht40_tx_power_diff[0].a = 0; in rtl8723bu_parse_efuse()
476 priv->ht40_tx_power_diff[0].b = 0; in rtl8723bu_parse_efuse()
479 priv->ofdm_tx_power_diff[i].a = in rtl8723bu_parse_efuse()
481 priv->ofdm_tx_power_diff[i].b = in rtl8723bu_parse_efuse()
484 priv->ht20_tx_power_diff[i].a = in rtl8723bu_parse_efuse()
486 priv->ht20_tx_power_diff[i].b = in rtl8723bu_parse_efuse()
489 priv->ht40_tx_power_diff[i].a = in rtl8723bu_parse_efuse()
491 priv->ht40_tx_power_diff[i].b = in rtl8723bu_parse_efuse()
495 priv->default_crystal_cap = priv->efuse_wifi.efuse8723bu.xtal_k & 0x3f; in rtl8723bu_parse_efuse()
497 dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name); in rtl8723bu_parse_efuse()
498 dev_info(&priv->udev->dev, "Product: %.41s\n", efuse->device_name); in rtl8723bu_parse_efuse()
503 static int rtl8723bu_load_firmware(struct rtl8xxxu_priv *priv) in rtl8723bu_load_firmware() argument
508 if (priv->enable_bluetooth) in rtl8723bu_load_firmware()
513 ret = rtl8xxxu_load_firmware(priv, fw_name); in rtl8723bu_load_firmware()
517 static void rtl8723bu_init_phy_bb(struct rtl8xxxu_priv *priv) in rtl8723bu_init_phy_bb() argument
522 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); in rtl8723bu_init_phy_bb()
524 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); in rtl8723bu_init_phy_bb()
526 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00); in rtl8723bu_init_phy_bb()
530 rtl8xxxu_write8(priv, REG_RF_CTRL, val8); in rtl8723bu_init_phy_bb()
533 rtl8xxxu_write8(priv, REG_SYS_FUNC, 0xe3); in rtl8723bu_init_phy_bb()
534 rtl8xxxu_write8(priv, REG_AFE_XTAL_CTRL + 1, 0x80); in rtl8723bu_init_phy_bb()
535 rtl8xxxu_init_phy_regs(priv, rtl8723b_phy_1t_init_table); in rtl8723bu_init_phy_bb()
537 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8723bu_table); in rtl8723bu_init_phy_bb()
540 static int rtl8723bu_init_phy_rf(struct rtl8xxxu_priv *priv) in rtl8723bu_init_phy_rf() argument
544 ret = rtl8xxxu_init_phy_rf(priv, rtl8723bu_radioa_1t_init_table, RF_A); in rtl8723bu_init_phy_rf()
548 rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdfbe0); in rtl8723bu_init_phy_rf()
549 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, 0x8c01); in rtl8723bu_init_phy_rf()
551 rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdffe0); in rtl8723bu_init_phy_rf()
556 void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv) in rtl8723bu_phy_init_antenna_selection() argument
560 val32 = rtl8xxxu_read32(priv, REG_PAD_CTRL1); in rtl8723bu_phy_init_antenna_selection()
562 rtl8xxxu_write32(priv, REG_PAD_CTRL1, val32); in rtl8723bu_phy_init_antenna_selection()
564 val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG); in rtl8723bu_phy_init_antenna_selection()
566 rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32); in rtl8723bu_phy_init_antenna_selection()
568 val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG); in rtl8723bu_phy_init_antenna_selection()
570 rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32); in rtl8723bu_phy_init_antenna_selection()
572 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); in rtl8723bu_phy_init_antenna_selection()
574 rtl8xxxu_write32(priv, REG_LEDCFG0, val32); in rtl8723bu_phy_init_antenna_selection()
576 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); in rtl8723bu_phy_init_antenna_selection()
578 rtl8xxxu_write32(priv, REG_LEDCFG0, val32); in rtl8723bu_phy_init_antenna_selection()
580 val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER); in rtl8723bu_phy_init_antenna_selection()
582 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32); in rtl8723bu_phy_init_antenna_selection()
584 val32 = rtl8xxxu_read32(priv, REG_RFE_CTRL_ANTA_SRC); in rtl8723bu_phy_init_antenna_selection()
587 rtl8xxxu_write32(priv, REG_RFE_CTRL_ANTA_SRC, val32); in rtl8723bu_phy_init_antenna_selection()
589 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA); in rtl8723bu_phy_init_antenna_selection()
591 rtl8xxxu_write32(priv, REG_PWR_DATA, val32); in rtl8723bu_phy_init_antenna_selection()
594 static int rtl8723bu_iqk_path_a(struct rtl8xxxu_priv *priv) in rtl8723bu_iqk_path_a() argument
599 path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); in rtl8723bu_iqk_path_a()
604 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_iqk_path_a()
606 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_iqk_path_a()
611 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); in rtl8723bu_iqk_path_a()
613 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); in rtl8723bu_iqk_path_a()
614 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000); in rtl8723bu_iqk_path_a()
615 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0003f); in rtl8723bu_iqk_path_a()
616 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xc7f87); in rtl8723bu_iqk_path_a()
621 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); in rtl8723bu_iqk_path_a()
622 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8723bu_iqk_path_a()
625 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); in rtl8723bu_iqk_path_a()
626 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); in rtl8723bu_iqk_path_a()
627 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); in rtl8723bu_iqk_path_a()
628 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); in rtl8723bu_iqk_path_a()
630 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821403ea); in rtl8723bu_iqk_path_a()
631 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000); in rtl8723bu_iqk_path_a()
632 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000); in rtl8723bu_iqk_path_a()
633 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000); in rtl8723bu_iqk_path_a()
636 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911); in rtl8723bu_iqk_path_a()
641 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_iqk_path_a()
644 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_iqk_path_a()
650 if (priv->rf_paths > 1) in rtl8723bu_iqk_path_a()
651 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000); in rtl8723bu_iqk_path_a()
653 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280); in rtl8723bu_iqk_path_a()
659 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800); in rtl8723bu_iqk_path_a()
662 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); in rtl8723bu_iqk_path_a()
663 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); in rtl8723bu_iqk_path_a()
668 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel); in rtl8723bu_iqk_path_a()
671 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800); in rtl8723bu_iqk_path_a()
677 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_iqk_path_a()
679 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_iqk_path_a()
682 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); in rtl8723bu_iqk_path_a()
683 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); in rtl8723bu_iqk_path_a()
684 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); in rtl8723bu_iqk_path_a()
704 static int rtl8723bu_rx_iqk_path_a(struct rtl8xxxu_priv *priv) in rtl8723bu_rx_iqk_path_a() argument
709 path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); in rtl8723bu_rx_iqk_path_a()
714 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_rx_iqk_path_a()
716 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_rx_iqk_path_a()
721 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); in rtl8723bu_rx_iqk_path_a()
723 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); in rtl8723bu_rx_iqk_path_a()
724 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); in rtl8723bu_rx_iqk_path_a()
725 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f); in rtl8723bu_rx_iqk_path_a()
726 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7); in rtl8723bu_rx_iqk_path_a()
731 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); in rtl8723bu_rx_iqk_path_a()
732 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8723bu_rx_iqk_path_a()
735 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); in rtl8723bu_rx_iqk_path_a()
736 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); in rtl8723bu_rx_iqk_path_a()
737 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); in rtl8723bu_rx_iqk_path_a()
738 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); in rtl8723bu_rx_iqk_path_a()
740 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160ff0); in rtl8723bu_rx_iqk_path_a()
741 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000); in rtl8723bu_rx_iqk_path_a()
742 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000); in rtl8723bu_rx_iqk_path_a()
743 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000); in rtl8723bu_rx_iqk_path_a()
746 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); in rtl8723bu_rx_iqk_path_a()
751 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_rx_iqk_path_a()
754 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_rx_iqk_path_a()
760 if (priv->rf_paths > 1) in rtl8723bu_rx_iqk_path_a()
761 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000); in rtl8723bu_rx_iqk_path_a()
763 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280); in rtl8723bu_rx_iqk_path_a()
769 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800); in rtl8723bu_rx_iqk_path_a()
772 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); in rtl8723bu_rx_iqk_path_a()
773 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); in rtl8723bu_rx_iqk_path_a()
778 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel); in rtl8723bu_rx_iqk_path_a()
781 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800); in rtl8723bu_rx_iqk_path_a()
787 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_rx_iqk_path_a()
789 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_rx_iqk_path_a()
792 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); in rtl8723bu_rx_iqk_path_a()
793 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); in rtl8723bu_rx_iqk_path_a()
794 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); in rtl8723bu_rx_iqk_path_a()
812 rtl8xxxu_write32(priv, REG_TX_IQK, val32); in rtl8723bu_rx_iqk_path_a()
817 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_rx_iqk_path_a()
819 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_rx_iqk_path_a()
820 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); in rtl8723bu_rx_iqk_path_a()
822 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); in rtl8723bu_rx_iqk_path_a()
823 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); in rtl8723bu_rx_iqk_path_a()
824 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f); in rtl8723bu_rx_iqk_path_a()
825 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7d77); in rtl8723bu_rx_iqk_path_a()
830 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0xf80); in rtl8723bu_rx_iqk_path_a()
831 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55, 0x4021f); in rtl8723bu_rx_iqk_path_a()
836 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); in rtl8723bu_rx_iqk_path_a()
839 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); in rtl8723bu_rx_iqk_path_a()
840 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c); in rtl8723bu_rx_iqk_path_a()
841 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); in rtl8723bu_rx_iqk_path_a()
842 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); in rtl8723bu_rx_iqk_path_a()
844 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82110000); in rtl8723bu_rx_iqk_path_a()
845 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x2816001f); in rtl8723bu_rx_iqk_path_a()
846 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000); in rtl8723bu_rx_iqk_path_a()
847 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000); in rtl8723bu_rx_iqk_path_a()
850 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a8d1); in rtl8723bu_rx_iqk_path_a()
855 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_rx_iqk_path_a()
858 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_rx_iqk_path_a()
860 if (priv->rf_paths > 1) in rtl8723bu_rx_iqk_path_a()
861 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000); in rtl8723bu_rx_iqk_path_a()
863 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280); in rtl8723bu_rx_iqk_path_a()
868 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800); in rtl8723bu_rx_iqk_path_a()
871 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); in rtl8723bu_rx_iqk_path_a()
872 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); in rtl8723bu_rx_iqk_path_a()
877 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel); in rtl8723bu_rx_iqk_path_a()
880 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800); in rtl8723bu_rx_iqk_path_a()
886 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_rx_iqk_path_a()
888 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_rx_iqk_path_a()
891 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); in rtl8723bu_rx_iqk_path_a()
892 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); in rtl8723bu_rx_iqk_path_a()
894 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x780); in rtl8723bu_rx_iqk_path_a()
913 static void rtl8723bu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, in rtl8723bu_phy_iqcalibrate() argument
916 struct device *dev = &priv->udev->dev; in rtl8723bu_phy_iqcalibrate()
940 u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff; in rtl8723bu_phy_iqcalibrate()
941 u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff; in rtl8723bu_phy_iqcalibrate()
950 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, in rtl8723bu_phy_iqcalibrate()
952 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); in rtl8723bu_phy_iqcalibrate()
953 rtl8xxxu_save_regs(priv, iqk_bb_regs, in rtl8723bu_phy_iqcalibrate()
954 priv->bb_backup, RTL8XXXU_BB_REGS); in rtl8723bu_phy_iqcalibrate()
957 rtl8xxxu_path_adda_on(priv, adda_regs, true); in rtl8723bu_phy_iqcalibrate()
960 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup); in rtl8723bu_phy_iqcalibrate()
962 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING); in rtl8723bu_phy_iqcalibrate()
964 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); in rtl8723bu_phy_iqcalibrate()
966 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); in rtl8723bu_phy_iqcalibrate()
967 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); in rtl8723bu_phy_iqcalibrate()
968 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000); in rtl8723bu_phy_iqcalibrate()
974 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_phy_iqcalibrate()
976 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_phy_iqcalibrate()
978 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); in rtl8723bu_phy_iqcalibrate()
980 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); in rtl8723bu_phy_iqcalibrate()
982 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); in rtl8723bu_phy_iqcalibrate()
983 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f); in rtl8723bu_phy_iqcalibrate()
984 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7); in rtl8723bu_phy_iqcalibrate()
986 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED); in rtl8723bu_phy_iqcalibrate()
988 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32); in rtl8723bu_phy_iqcalibrate()
990 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_43, 0x60fbd); in rtl8723bu_phy_iqcalibrate()
993 path_a_ok = rtl8723bu_iqk_path_a(priv); in rtl8723bu_phy_iqcalibrate()
995 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_phy_iqcalibrate()
997 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_phy_iqcalibrate()
999 val32 = rtl8xxxu_read32(priv, in rtl8723bu_phy_iqcalibrate()
1002 val32 = rtl8xxxu_read32(priv, in rtl8723bu_phy_iqcalibrate()
1014 path_a_ok = rtl8723bu_rx_iqk_path_a(priv); in rtl8723bu_phy_iqcalibrate()
1016 val32 = rtl8xxxu_read32(priv, in rtl8723bu_phy_iqcalibrate()
1019 val32 = rtl8xxxu_read32(priv, in rtl8723bu_phy_iqcalibrate()
1030 if (priv->tx_paths > 1) { in rtl8723bu_phy_iqcalibrate()
1038 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_phy_iqcalibrate()
1040 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_phy_iqcalibrate()
1041 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000); in rtl8723bu_phy_iqcalibrate()
1043 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_phy_iqcalibrate()
1046 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_phy_iqcalibrate()
1049 rtl8xxxu_path_adda_on(priv, adda_regs, false); in rtl8723bu_phy_iqcalibrate()
1052 path_b_ok = rtl8xxxu_iqk_path_b(priv); in rtl8723bu_phy_iqcalibrate()
1054 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); in rtl8723bu_phy_iqcalibrate()
1056 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); in rtl8723bu_phy_iqcalibrate()
1066 path_b_ok = rtl8723bu_rx_iqk_path_b(priv); in rtl8723bu_phy_iqcalibrate()
1068 val32 = rtl8xxxu_read32(priv, in rtl8723bu_phy_iqcalibrate()
1071 val32 = rtl8xxxu_read32(priv, in rtl8723bu_phy_iqcalibrate()
1084 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_phy_iqcalibrate()
1086 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_phy_iqcalibrate()
1090 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, in rtl8723bu_phy_iqcalibrate()
1094 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); in rtl8723bu_phy_iqcalibrate()
1097 rtl8xxxu_restore_regs(priv, iqk_bb_regs, in rtl8723bu_phy_iqcalibrate()
1098 priv->bb_backup, RTL8XXXU_BB_REGS); in rtl8723bu_phy_iqcalibrate()
1101 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); in rtl8723bu_phy_iqcalibrate()
1103 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50); in rtl8723bu_phy_iqcalibrate()
1104 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc); in rtl8723bu_phy_iqcalibrate()
1106 if (priv->tx_paths > 1) { in rtl8723bu_phy_iqcalibrate()
1107 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1); in rtl8723bu_phy_iqcalibrate()
1109 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1, in rtl8723bu_phy_iqcalibrate()
1111 rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1, in rtl8723bu_phy_iqcalibrate()
1116 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); in rtl8723bu_phy_iqcalibrate()
1117 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); in rtl8723bu_phy_iqcalibrate()
1121 static void rtl8723bu_phy_iq_calibrate(struct rtl8xxxu_priv *priv) in rtl8723bu_phy_iq_calibrate() argument
1123 struct device *dev = &priv->udev->dev; in rtl8723bu_phy_iq_calibrate()
1133 rtl8xxxu_gen2_prepare_calibrate(priv, 1); in rtl8723bu_phy_iq_calibrate()
1141 bt_control = rtl8xxxu_read32(priv, REG_BT_CONTROL_8723BU); in rtl8723bu_phy_iq_calibrate()
1144 rtl8723bu_phy_iqcalibrate(priv, result, i); in rtl8723bu_phy_iq_calibrate()
1147 simu = rtl8xxxu_gen2_simularity_compare(priv, in rtl8723bu_phy_iq_calibrate()
1156 simu = rtl8xxxu_gen2_simularity_compare(priv, in rtl8723bu_phy_iq_calibrate()
1163 simu = rtl8xxxu_gen2_simularity_compare(priv, in rtl8723bu_phy_iq_calibrate()
1192 priv->rege94 = reg_e94; in rtl8723bu_phy_iq_calibrate()
1194 priv->rege9c = reg_e9c; in rtl8723bu_phy_iq_calibrate()
1198 priv->regeb4 = reg_eb4; in rtl8723bu_phy_iq_calibrate()
1200 priv->regebc = reg_ebc; in rtl8723bu_phy_iq_calibrate()
1211 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100; in rtl8723bu_phy_iq_calibrate()
1212 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0; in rtl8723bu_phy_iq_calibrate()
1216 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, in rtl8723bu_phy_iq_calibrate()
1219 if (priv->tx_paths > 1 && reg_eb4) in rtl8723bu_phy_iq_calibrate()
1220 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result, in rtl8723bu_phy_iq_calibrate()
1223 rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg, in rtl8723bu_phy_iq_calibrate()
1224 priv->bb_recovery_backup, RTL8XXXU_BB_REGS); in rtl8723bu_phy_iq_calibrate()
1226 rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, bt_control); in rtl8723bu_phy_iq_calibrate()
1228 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); in rtl8723bu_phy_iq_calibrate()
1230 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); in rtl8723bu_phy_iq_calibrate()
1231 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x18000); in rtl8723bu_phy_iq_calibrate()
1232 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f); in rtl8723bu_phy_iq_calibrate()
1233 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xe6177); in rtl8723bu_phy_iq_calibrate()
1234 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED); in rtl8723bu_phy_iq_calibrate()
1236 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32); in rtl8723bu_phy_iq_calibrate()
1237 rtl8xxxu_write_rfreg(priv, RF_A, 0x43, 0x300bd); in rtl8723bu_phy_iq_calibrate()
1239 if (priv->rf_paths > 1) in rtl8723bu_phy_iq_calibrate()
1242 rtl8xxxu_gen2_prepare_calibrate(priv, 0); in rtl8723bu_phy_iq_calibrate()
1245 static int rtl8723bu_active_to_emu(struct rtl8xxxu_priv *priv) in rtl8723bu_active_to_emu() argument
1253 rtl8xxxu_write8(priv, REG_RF_CTRL, 0); in rtl8723bu_active_to_emu()
1256 val16 = rtl8xxxu_read16(priv, REG_GPIO_INTM); in rtl8723bu_active_to_emu()
1258 rtl8xxxu_write16(priv, REG_GPIO_INTM, val16); in rtl8723bu_active_to_emu()
1261 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8723bu_active_to_emu()
1263 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8723bu_active_to_emu()
1266 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); in rtl8723bu_active_to_emu()
1268 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); in rtl8723bu_active_to_emu()
1271 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); in rtl8723bu_active_to_emu()
1278 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n", in rtl8723bu_active_to_emu()
1285 val8 = rtl8xxxu_read8(priv, REG_AFE_MISC); in rtl8723bu_active_to_emu()
1287 rtl8xxxu_write8(priv, REG_AFE_MISC, val8); in rtl8723bu_active_to_emu()
1290 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); in rtl8723bu_active_to_emu()
1292 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); in rtl8723bu_active_to_emu()
1295 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL); in rtl8723bu_active_to_emu()
1297 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8); in rtl8723bu_active_to_emu()
1303 static int rtl8723b_emu_to_active(struct rtl8xxxu_priv *priv) in rtl8723b_emu_to_active() argument
1310 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL); in rtl8723b_emu_to_active()
1312 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8); in rtl8723b_emu_to_active()
1315 val8 = rtl8xxxu_read8(priv, 0x0067); in rtl8723b_emu_to_active()
1317 rtl8xxxu_write8(priv, 0x0067, val8); in rtl8723b_emu_to_active()
1322 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); in rtl8723b_emu_to_active()
1324 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); in rtl8723b_emu_to_active()
1327 val32 = rtl8xxxu_read8(priv, REG_APS_FSMCO); in rtl8723b_emu_to_active()
1329 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8723b_emu_to_active()
1333 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8723b_emu_to_active()
1348 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8723b_emu_to_active()
1350 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8723b_emu_to_active()
1353 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8723b_emu_to_active()
1355 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8723b_emu_to_active()
1358 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8723b_emu_to_active()
1360 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8723b_emu_to_active()
1363 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8723b_emu_to_active()
1365 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8723b_emu_to_active()
1368 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); in rtl8723b_emu_to_active()
1382 val8 = rtl8xxxu_read8(priv, REG_AFE_MISC); in rtl8723b_emu_to_active()
1384 rtl8xxxu_write8(priv, REG_AFE_MISC, val8); in rtl8723b_emu_to_active()
1387 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 1); in rtl8723b_emu_to_active()
1389 rtl8xxxu_write8(priv, REG_GPIO_INTM + 1, val8); in rtl8723b_emu_to_active()
1392 val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2 + 1); in rtl8723b_emu_to_active()
1394 rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2 + 1, val8); in rtl8723b_emu_to_active()
1397 val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2); in rtl8723b_emu_to_active()
1399 rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2, val8); in rtl8723b_emu_to_active()
1402 val8 = rtl8xxxu_read8(priv, REG_HSIMR); in rtl8723b_emu_to_active()
1404 rtl8xxxu_write8(priv, REG_HSIMR, val8); in rtl8723b_emu_to_active()
1407 val8 = rtl8xxxu_read8(priv, REG_HSIMR + 2); in rtl8723b_emu_to_active()
1409 rtl8xxxu_write8(priv, REG_HSIMR + 2, val8); in rtl8723b_emu_to_active()
1411 val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL); in rtl8723b_emu_to_active()
1413 rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL, val8); in rtl8723b_emu_to_active()
1416 val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL + 1); in rtl8723b_emu_to_active()
1418 rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL + 1, val8); in rtl8723b_emu_to_active()
1424 static int rtl8723bu_power_on(struct rtl8xxxu_priv *priv) in rtl8723bu_power_on() argument
1431 rtl8xxxu_disabled_to_emu(priv); in rtl8723bu_power_on()
1433 ret = rtl8723b_emu_to_active(priv); in rtl8723bu_power_on()
1441 val16 = rtl8xxxu_read16(priv, REG_CR); in rtl8723bu_power_on()
1447 rtl8xxxu_write16(priv, REG_CR, val16); in rtl8723bu_power_on()
1453 rtl8xxxu_write8(priv, REG_PAD_CTRL1 + 3, 0x20); in rtl8723bu_power_on()
1455 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); in rtl8723bu_power_on()
1457 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); in rtl8723bu_power_on()
1459 rtl8xxxu_write8(priv, REG_BT_CONTROL_8723BU + 1, 0x18); in rtl8723bu_power_on()
1460 rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04); in rtl8723bu_power_on()
1461 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00); in rtl8723bu_power_on()
1463 rtl8xxxu_write8(priv, 0xfe08, 0x01); in rtl8723bu_power_on()
1465 val16 = rtl8xxxu_read16(priv, REG_PWR_DATA); in rtl8723bu_power_on()
1467 rtl8xxxu_write16(priv, REG_PWR_DATA, val16); in rtl8723bu_power_on()
1469 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); in rtl8723bu_power_on()
1471 rtl8xxxu_write32(priv, REG_LEDCFG0, val32); in rtl8723bu_power_on()
1473 val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1); in rtl8723bu_power_on()
1475 rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8); in rtl8723bu_power_on()
1480 static void rtl8723bu_power_off(struct rtl8xxxu_priv *priv) in rtl8723bu_power_off() argument
1485 rtl8xxxu_flush_fifo(priv); in rtl8723bu_power_off()
1490 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL); in rtl8723bu_power_off()
1492 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8); in rtl8723bu_power_off()
1494 rtl8xxxu_write8(priv, REG_CR, 0x0000); in rtl8723bu_power_off()
1496 rtl8xxxu_active_to_lps(priv); in rtl8723bu_power_off()
1499 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) in rtl8723bu_power_off()
1500 rtl8xxxu_firmware_self_reset(priv); in rtl8723bu_power_off()
1503 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); in rtl8723bu_power_off()
1505 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); in rtl8723bu_power_off()
1508 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); in rtl8723bu_power_off()
1510 rtl8723bu_active_to_emu(priv); in rtl8723bu_power_off()
1512 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); in rtl8723bu_power_off()
1514 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); in rtl8723bu_power_off()
1517 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2); in rtl8723bu_power_off()
1519 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8); in rtl8723bu_power_off()
1522 static void rtl8723b_enable_rf(struct rtl8xxxu_priv *priv) in rtl8723b_enable_rf() argument
1528 val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA); in rtl8723b_enable_rf()
1530 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32); in rtl8723b_enable_rf()
1536 rtl8xxxu_write8(priv, 0x0790, 0x05); in rtl8723b_enable_rf()
1542 rtl8xxxu_write8(priv, 0x0778, 0x01); in rtl8723b_enable_rf()
1544 val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG); in rtl8723b_enable_rf()
1546 rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8); in rtl8723b_enable_rf()
1548 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_IQADJ_G1, 0x780); in rtl8723b_enable_rf()
1550 rtl8723bu_write_btreg(priv, 0x3c, 0x15); /* BT TRx Mask on */ in rtl8723b_enable_rf()
1558 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_grant)); in rtl8723b_enable_rf()
1563 rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x0c); in rtl8723b_enable_rf()
1568 val8 = rtl8xxxu_read8(priv, 0x0067); in rtl8723b_enable_rf()
1570 rtl8xxxu_write8(priv, 0x0067, val8); in rtl8723b_enable_rf()
1572 val32 = rtl8xxxu_read32(priv, REG_PWR_DATA); in rtl8723b_enable_rf()
1574 rtl8xxxu_write32(priv, REG_PWR_DATA, val32); in rtl8723b_enable_rf()
1579 rtl8xxxu_write8(priv, 0x0974, 0xff); in rtl8723b_enable_rf()
1581 val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER); in rtl8723b_enable_rf()
1583 rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32); in rtl8723b_enable_rf()
1585 rtl8xxxu_write8(priv, REG_RFE_CTRL_ANTA_SRC, 0x77); in rtl8723b_enable_rf()
1587 val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); in rtl8723b_enable_rf()
1590 rtl8xxxu_write32(priv, REG_LEDCFG0, val32); in rtl8723b_enable_rf()
1595 val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1); in rtl8723b_enable_rf()
1597 rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8); in rtl8723b_enable_rf()
1603 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.ant_sel_rsv)); in rtl8723b_enable_rf()
1613 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x80); in rtl8723b_enable_rf()
1618 rtl8723bu_set_ps_tdma(priv, 0x08, 0x00, 0x00, 0x00, 0x00); in rtl8723b_enable_rf()
1620 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555); in rtl8723b_enable_rf()
1621 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x55555555); in rtl8723b_enable_rf()
1622 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); in rtl8723b_enable_rf()
1623 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); in rtl8723b_enable_rf()
1628 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_info)); in rtl8723b_enable_rf()
1633 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.ignore_wlan)); in rtl8723b_enable_rf()
1636 static void rtl8723bu_init_aggregation(struct rtl8xxxu_priv *priv) in rtl8723bu_init_aggregation() argument
1644 agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL); in rtl8723bu_init_aggregation()
1647 agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH); in rtl8723bu_init_aggregation()
1651 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); in rtl8723bu_init_aggregation()
1652 rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx); in rtl8723bu_init_aggregation()
1655 static void rtl8723bu_init_statistics(struct rtl8xxxu_priv *priv) in rtl8723bu_init_statistics() argument
1660 rtl8xxxu_write16(priv, REG_NHM_TIMER_8723B + 2, 0x2710); in rtl8723bu_init_statistics()
1661 rtl8xxxu_write16(priv, REG_NHM_TH9_TH10_8723B + 2, 0xffff); in rtl8723bu_init_statistics()
1662 rtl8xxxu_write32(priv, REG_NHM_TH3_TO_TH0_8723B, 0xffffff52); in rtl8723bu_init_statistics()
1663 rtl8xxxu_write32(priv, REG_NHM_TH7_TO_TH4_8723B, 0xffffffff); in rtl8723bu_init_statistics()
1665 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_init_statistics()
1667 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_init_statistics()
1669 val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B); in rtl8723bu_init_statistics()
1671 rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val32); in rtl8723bu_init_statistics()
1673 val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC); in rtl8723bu_init_statistics()
1675 rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32); in rtl8723bu_init_statistics()
1678 static s8 rtl8723b_cck_rssi(struct rtl8xxxu_priv *priv, u8 cck_agc_rpt) in rtl8723b_cck_rssi() argument