Lines Matching refs:rtlpriv
27 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92ee_set_bcn_ctrl_reg() local
32 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val); in _rtl92ee_set_bcn_ctrl_reg()
37 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92ee_stop_tx_beacon() local
40 tmp = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); in _rtl92ee_stop_tx_beacon()
41 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp & (~BIT(6))); in _rtl92ee_stop_tx_beacon()
42 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); in _rtl92ee_stop_tx_beacon()
43 tmp = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); in _rtl92ee_stop_tx_beacon()
45 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp); in _rtl92ee_stop_tx_beacon()
50 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92ee_resume_tx_beacon() local
53 tmp = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); in _rtl92ee_resume_tx_beacon()
54 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp | BIT(6)); in _rtl92ee_resume_tx_beacon()
55 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); in _rtl92ee_resume_tx_beacon()
56 tmp = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2); in _rtl92ee_resume_tx_beacon()
58 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp); in _rtl92ee_resume_tx_beacon()
74 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92ee_set_fw_clock_on() local
80 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN, in _rtl92ee_set_fw_clock_on()
85 if (!rtlpriv->psc.fw_current_inpsmode) in _rtl92ee_set_fw_clock_on()
89 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); in _rtl92ee_set_fw_clock_on()
92 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); in _rtl92ee_set_fw_clock_on()
97 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); in _rtl92ee_set_fw_clock_on()
99 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); in _rtl92ee_set_fw_clock_on()
102 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); in _rtl92ee_set_fw_clock_on()
108 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM, in _rtl92ee_set_fw_clock_on()
112 content = rtl_read_dword(rtlpriv, isr_regaddr); in _rtl92ee_set_fw_clock_on()
116 content = rtl_read_dword(rtlpriv, isr_regaddr); in _rtl92ee_set_fw_clock_on()
120 rtl_write_word(rtlpriv, isr_regaddr, 0x0100); in _rtl92ee_set_fw_clock_on()
122 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, in _rtl92ee_set_fw_clock_on()
128 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); in _rtl92ee_set_fw_clock_on()
130 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); in _rtl92ee_set_fw_clock_on()
132 mod_timer(&rtlpriv->works.fw_clockoff_timer, in _rtl92ee_set_fw_clock_on()
136 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); in _rtl92ee_set_fw_clock_on()
138 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); in _rtl92ee_set_fw_clock_on()
144 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92ee_set_fw_clock_off() local
154 if (!rtlpriv->psc.fw_current_inpsmode) in _rtl92ee_set_fw_clock_off()
159 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate)); in _rtl92ee_set_fw_clock_off()
160 if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF) in _rtl92ee_set_fw_clock_off()
172 mod_timer(&rtlpriv->works.fw_clockoff_timer, in _rtl92ee_set_fw_clock_off()
178 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); in _rtl92ee_set_fw_clock_off()
181 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); in _rtl92ee_set_fw_clock_off()
183 rtl_write_word(rtlpriv, REG_HISR, 0x0100); in _rtl92ee_set_fw_clock_off()
184 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, in _rtl92ee_set_fw_clock_off()
186 spin_lock_bh(&rtlpriv->locks.fw_ps_lock); in _rtl92ee_set_fw_clock_off()
188 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); in _rtl92ee_set_fw_clock_off()
190 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock); in _rtl92ee_set_fw_clock_off()
191 mod_timer(&rtlpriv->works.fw_clockoff_timer, in _rtl92ee_set_fw_clock_off()
222 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92ee_fwlps_leave() local
232 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, in _rtl92ee_fwlps_leave()
234 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, in _rtl92ee_fwlps_leave()
238 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, in _rtl92ee_fwlps_leave()
240 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, in _rtl92ee_fwlps_leave()
242 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, in _rtl92ee_fwlps_leave()
249 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92ee_fwlps_enter() local
257 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, in _rtl92ee_fwlps_enter()
259 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, in _rtl92ee_fwlps_enter()
265 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS, in _rtl92ee_fwlps_enter()
267 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE, in _rtl92ee_fwlps_enter()
269 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, in _rtl92ee_fwlps_enter()
276 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92ee_get_hw_reg() local
291 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, in rtl92ee_get_hw_reg()
296 val_rcr = rtl_read_dword(rtlpriv, REG_RCR); in rtl92ee_get_hw_reg()
313 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4)); in rtl92ee_get_hw_reg()
314 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR); in rtl92ee_get_hw_reg()
322 rtl_dbg(rtlpriv, COMP_ERR, DBG_DMESG, in rtl92ee_get_hw_reg()
330 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92ee_download_rsvd_page() local
337 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1); in _rtl92ee_download_rsvd_page()
338 rtl_write_byte(rtlpriv, REG_CR + 1, tmp_regcr | BIT(0)); in _rtl92ee_download_rsvd_page()
351 tmp_reg422 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2); in _rtl92ee_download_rsvd_page()
352 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422 & (~BIT(6))); in _rtl92ee_download_rsvd_page()
359 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_DWBCN0_CTRL + 2); in _rtl92ee_download_rsvd_page()
360 rtl_write_byte(rtlpriv, REG_DWBCN0_CTRL + 2, in _rtl92ee_download_rsvd_page()
366 txbc_reg = rtl_read_byte(rtlpriv, REG_MGQ_TXBD_NUM + 3); in _rtl92ee_download_rsvd_page()
371 txbc_reg = rtl_read_byte(rtlpriv, REG_MGQ_TXBD_NUM + 3); in _rtl92ee_download_rsvd_page()
373 rtl_write_byte(rtlpriv, REG_MGQ_TXBD_NUM + 3, in _rtl92ee_download_rsvd_page()
377 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_DWBCN0_CTRL + 2); in _rtl92ee_download_rsvd_page()
382 bcnvalid_reg = rtl_read_byte(rtlpriv, in _rtl92ee_download_rsvd_page()
387 rtl_write_byte(rtlpriv, REG_DWBCN0_CTRL + 2, BIT(0)); in _rtl92ee_download_rsvd_page()
393 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, in _rtl92ee_download_rsvd_page()
401 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422); in _rtl92ee_download_rsvd_page()
403 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1); in _rtl92ee_download_rsvd_page()
404 rtl_write_byte(rtlpriv, REG_CR + 1, tmp_regcr & (~BIT(0))); in _rtl92ee_download_rsvd_page()
409 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92ee_set_hw_reg() local
419 rtl_write_byte(rtlpriv, (REG_MACID + idx), val[idx]); in rtl92ee_set_hw_reg()
427 rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff); in rtl92ee_set_hw_reg()
428 rtl_write_byte(rtlpriv, REG_RRSR + 1, (b_rate_cfg >> 8) & 0xff); in rtl92ee_set_hw_reg()
432 rtl_write_byte(rtlpriv, (REG_BSSID + idx), val[idx]); in rtl92ee_set_hw_reg()
435 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]); in rtl92ee_set_hw_reg()
436 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]); in rtl92ee_set_hw_reg()
438 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]); in rtl92ee_set_hw_reg()
439 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]); in rtl92ee_set_hw_reg()
442 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 0x0e0e); in rtl92ee_set_hw_reg()
444 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, in rtl92ee_set_hw_reg()
450 rtl_dbg(rtlpriv, COMP_MLME, DBG_TRACE, in rtl92ee_set_hw_reg()
453 rtl_write_byte(rtlpriv, REG_SLOT, val[0]); in rtl92ee_set_hw_reg()
456 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM, in rtl92ee_set_hw_reg()
464 reg_tmp = (rtlpriv->mac80211.cur_40_prime_sc) << 5; in rtl92ee_set_hw_reg()
467 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp); in rtl92ee_set_hw_reg()
468 rtlpriv->mac80211.short_preamble = short_preamble; in rtl92ee_set_hw_reg()
472 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val)); in rtl92ee_set_hw_reg()
493 rtl_write_byte(rtlpriv, in rtl92ee_set_hw_reg()
497 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD, in rtl92ee_set_hw_reg()
506 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL, in rtl92ee_set_hw_reg()
515 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL); in rtl92ee_set_hw_reg()
531 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, in rtl92ee_set_hw_reg()
548 rtl_dbg(rtlpriv, COMP_ERR, DBG_DMESG, in rtl92ee_set_hw_reg()
555 rtl_dbg(rtlpriv, COMP_QOS, DBG_TRACE, in rtl92ee_set_hw_reg()
558 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl); in rtl92ee_set_hw_reg()
562 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]); in rtl92ee_set_hw_reg()
569 rtl_write_word(rtlpriv, REG_RETRY_LIMIT, in rtl92ee_set_hw_reg()
575 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1))); in rtl92ee_set_hw_reg()
589 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM); in rtl92ee_set_hw_reg()
593 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, (*(u8 *)val)); in rtl92ee_set_hw_reg()
595 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, in rtl92ee_set_hw_reg()
622 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL); in rtl92ee_set_hw_reg()
634 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT); in rtl92ee_set_hw_reg()
636 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, in rtl92ee_set_hw_reg()
648 rtl_write_dword(rtlpriv, REG_TSFTR, in rtl92ee_set_hw_reg()
650 rtl_write_dword(rtlpriv, REG_TSFTR + 4, in rtl92ee_set_hw_reg()
668 rtl_dbg(rtlpriv, COMP_ERR, DBG_DMESG, in rtl92ee_set_hw_reg()
676 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92ee_llt_table_init() local
682 rtl_write_dword(rtlpriv, REG_RQPN, 0x80E60808); in _rtl92ee_llt_table_init()
684 rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy); in _rtl92ee_llt_table_init()
685 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x3d00 - 1); in _rtl92ee_llt_table_init()
687 rtl_write_byte(rtlpriv, REG_DWBCN0_CTRL + 1, txpktbuf_bndy); in _rtl92ee_llt_table_init()
688 rtl_write_byte(rtlpriv, REG_DWBCN1_CTRL + 1, txpktbuf_bndy); in _rtl92ee_llt_table_init()
690 rtl_write_byte(rtlpriv, REG_BCNQ_BDNY, txpktbuf_bndy); in _rtl92ee_llt_table_init()
691 rtl_write_byte(rtlpriv, REG_BCNQ1_BDNY, txpktbuf_bndy); in _rtl92ee_llt_table_init()
693 rtl_write_byte(rtlpriv, REG_MGQ_BDNY, txpktbuf_bndy); in _rtl92ee_llt_table_init()
694 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy); in _rtl92ee_llt_table_init()
696 rtl_write_byte(rtlpriv, REG_PBP, 0x31); in _rtl92ee_llt_table_init()
697 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4); in _rtl92ee_llt_table_init()
699 u8tmp = rtl_read_byte(rtlpriv, REG_AUTO_LLT + 2); in _rtl92ee_llt_table_init()
700 rtl_write_byte(rtlpriv, REG_AUTO_LLT + 2, u8tmp | BIT(0)); in _rtl92ee_llt_table_init()
703 u8tmp = rtl_read_byte(rtlpriv, REG_AUTO_LLT + 2); in _rtl92ee_llt_table_init()
715 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92ee_gen_refresh_led_state() local
717 struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0; in _rtl92ee_gen_refresh_led_state()
719 if (rtlpriv->rtlhal.up_first_time) in _rtl92ee_gen_refresh_led_state()
732 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92ee_init_mac() local
740 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0); in _rtl92ee_init_mac()
742 dwordtmp = rtl_read_dword(rtlpriv, REG_SYS_CFG1); in _rtl92ee_init_mac()
744 rtl_write_byte(rtlpriv, 0x7c, 0xc3); in _rtl92ee_init_mac()
746 bytetmp = rtl_read_byte(rtlpriv, 0x16); in _rtl92ee_init_mac()
747 rtl_write_byte(rtlpriv, 0x16, bytetmp | BIT(4) | BIT(6)); in _rtl92ee_init_mac()
748 rtl_write_byte(rtlpriv, 0x7c, 0x83); in _rtl92ee_init_mac()
751 bytetmp = rtl_read_byte(rtlpriv, REG_AFE_CTRL2); in _rtl92ee_init_mac()
753 rtl_write_byte(rtlpriv, REG_AFE_CTRL2, bytetmp); in _rtl92ee_init_mac()
755 dwordtmp = rtl_read_dword(rtlpriv, REG_AFE_CTRL4); in _rtl92ee_init_mac()
757 rtl_write_dword(rtlpriv, REG_AFE_CTRL4, dwordtmp); in _rtl92ee_init_mac()
762 bytetmp = rtl_read_byte(rtlpriv, REG_AFE_CTRL2); in _rtl92ee_init_mac()
764 rtl_write_byte(rtlpriv, REG_AFE_CTRL2, bytetmp); in _rtl92ee_init_mac()
766 dwordtmp = rtl_read_dword(rtlpriv, REG_AFE_CTRL4); in _rtl92ee_init_mac()
768 rtl_write_dword(rtlpriv, REG_AFE_CTRL4, dwordtmp); in _rtl92ee_init_mac()
771 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, in _rtl92ee_init_mac()
774 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, in _rtl92ee_init_mac()
780 bytetmp = rtl_read_byte(rtlpriv, REG_CR); in _rtl92ee_init_mac()
782 rtl_write_byte(rtlpriv, REG_CR, bytetmp); in _rtl92ee_init_mac()
785 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, bytetmp); in _rtl92ee_init_mac()
789 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR); in _rtl92ee_init_mac()
790 rtl_write_byte(rtlpriv, REG_SYS_CLKR, bytetmp | BIT(3)); in _rtl92ee_init_mac()
791 bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG + 1); in _rtl92ee_init_mac()
792 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp & (~BIT(4))); in _rtl92ee_init_mac()
794 rtl_write_word(rtlpriv, REG_CR, 0x2ff); in _rtl92ee_init_mac()
798 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, in _rtl92ee_init_mac()
804 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff); in _rtl92ee_init_mac()
805 rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff); in _rtl92ee_init_mac()
807 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL); in _rtl92ee_init_mac()
810 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp); in _rtl92ee_init_mac()
812 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F); in _rtl92ee_init_mac()
815 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); in _rtl92ee_init_mac()
816 rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xffff); in _rtl92ee_init_mac()
819 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config); in _rtl92ee_init_mac()
822 if (!rtlpriv->cfg->mod_params->dma64) in _rtl92ee_init_mac()
825 rtl_write_dword(rtlpriv, REG_BCNQ_DESA + 4, in _rtl92ee_init_mac()
828 rtl_write_dword(rtlpriv, REG_MGQ_DESA + 4, in _rtl92ee_init_mac()
830 rtl_write_dword(rtlpriv, REG_VOQ_DESA + 4, in _rtl92ee_init_mac()
832 rtl_write_dword(rtlpriv, REG_VIQ_DESA + 4, in _rtl92ee_init_mac()
834 rtl_write_dword(rtlpriv, REG_BEQ_DESA + 4, in _rtl92ee_init_mac()
836 rtl_write_dword(rtlpriv, REG_BKQ_DESA + 4, in _rtl92ee_init_mac()
838 rtl_write_dword(rtlpriv, REG_HQ0_DESA + 4, in _rtl92ee_init_mac()
841 rtl_write_dword(rtlpriv, REG_RX_DESA + 4, in _rtl92ee_init_mac()
847 rtl_write_dword(rtlpriv, REG_BCNQ_DESA, in _rtl92ee_init_mac()
850 rtl_write_dword(rtlpriv, REG_MGQ_DESA, in _rtl92ee_init_mac()
853 rtl_write_dword(rtlpriv, REG_VOQ_DESA, in _rtl92ee_init_mac()
856 rtl_write_dword(rtlpriv, REG_VIQ_DESA, in _rtl92ee_init_mac()
860 rtl_write_dword(rtlpriv, REG_BEQ_DESA, in _rtl92ee_init_mac()
864 dwordtmp = rtl_read_dword(rtlpriv, REG_BEQ_DESA); in _rtl92ee_init_mac()
866 rtl_write_dword(rtlpriv, REG_BKQ_DESA, in _rtl92ee_init_mac()
869 rtl_write_dword(rtlpriv, REG_HQ0_DESA, in _rtl92ee_init_mac()
873 rtl_write_dword(rtlpriv, REG_RX_DESA, in _rtl92ee_init_mac()
881 rtl_write_dword(rtlpriv, REG_TSFTIMER_HCI, 0x3fffffff); in _rtl92ee_init_mac()
883 bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 3); in _rtl92ee_init_mac()
884 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, bytetmp | 0xF7); in _rtl92ee_init_mac()
886 rtl_write_dword(rtlpriv, REG_INT_MIG, 0); in _rtl92ee_init_mac()
888 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0); in _rtl92ee_init_mac()
890 rtl_write_word(rtlpriv, REG_MGQ_TXBD_NUM, in _rtl92ee_init_mac()
892 rtl_write_word(rtlpriv, REG_VOQ_TXBD_NUM, in _rtl92ee_init_mac()
894 rtl_write_word(rtlpriv, REG_VIQ_TXBD_NUM, in _rtl92ee_init_mac()
896 rtl_write_word(rtlpriv, REG_BEQ_TXBD_NUM, in _rtl92ee_init_mac()
898 rtl_write_word(rtlpriv, REG_VOQ_TXBD_NUM, in _rtl92ee_init_mac()
900 rtl_write_word(rtlpriv, REG_BKQ_TXBD_NUM, in _rtl92ee_init_mac()
902 rtl_write_word(rtlpriv, REG_HI0Q_TXBD_NUM, in _rtl92ee_init_mac()
904 rtl_write_word(rtlpriv, REG_HI1Q_TXBD_NUM, in _rtl92ee_init_mac()
906 rtl_write_word(rtlpriv, REG_HI2Q_TXBD_NUM, in _rtl92ee_init_mac()
908 rtl_write_word(rtlpriv, REG_HI3Q_TXBD_NUM, in _rtl92ee_init_mac()
910 rtl_write_word(rtlpriv, REG_HI4Q_TXBD_NUM, in _rtl92ee_init_mac()
912 rtl_write_word(rtlpriv, REG_HI5Q_TXBD_NUM, in _rtl92ee_init_mac()
914 rtl_write_word(rtlpriv, REG_HI6Q_TXBD_NUM, in _rtl92ee_init_mac()
916 rtl_write_word(rtlpriv, REG_HI7Q_TXBD_NUM, in _rtl92ee_init_mac()
919 rtl_write_word(rtlpriv, REG_RX_RXBD_NUM, in _rtl92ee_init_mac()
923 rtl_write_dword(rtlpriv, REG_TSFTIMER_HCI, 0XFFFFFFFF); in _rtl92ee_init_mac()
931 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92ee_hw_configure() local
937 rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr); in _rtl92ee_hw_configure()
940 rtl_write_dword(rtlpriv, REG_ARFR0, 0x00000010); in _rtl92ee_hw_configure()
941 rtl_write_dword(rtlpriv, REG_ARFR0 + 4, 0x3e0ff000); in _rtl92ee_hw_configure()
944 rtl_write_dword(rtlpriv, REG_ARFR1, 0x00000010); in _rtl92ee_hw_configure()
945 rtl_write_dword(rtlpriv, REG_ARFR1 + 4, 0x000ff000); in _rtl92ee_hw_configure()
948 rtl_write_byte(rtlpriv, REG_SLOT, 0x09); in _rtl92ee_hw_configure()
951 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80); in _rtl92ee_hw_configure()
954 rtl_write_word(rtlpriv, REG_RETRY_LIMIT, 0x0707); in _rtl92ee_hw_configure()
957 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x0201ffff); in _rtl92ee_hw_configure()
960 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000); in _rtl92ee_hw_configure()
961 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504); in _rtl92ee_hw_configure()
962 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000); in _rtl92ee_hw_configure()
963 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504); in _rtl92ee_hw_configure()
966 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2); in _rtl92ee_hw_configure()
967 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff); in _rtl92ee_hw_configure()
970 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val); in _rtl92ee_hw_configure()
977 rtl_write_byte(rtlpriv, REG_BCN_CTRL_1, 0); in _rtl92ee_hw_configure()
980 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); /* 8 ms */ in _rtl92ee_hw_configure()
982 rtl_write_byte(rtlpriv, REG_PIFS, 0); in _rtl92ee_hw_configure()
983 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16); in _rtl92ee_hw_configure()
985 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040); in _rtl92ee_hw_configure()
986 rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x08ff); in _rtl92ee_hw_configure()
989 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666); in _rtl92ee_hw_configure()
992 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40); in _rtl92ee_hw_configure()
995 rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x100a); in _rtl92ee_hw_configure()
996 rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x100a); in _rtl92ee_hw_configure()
999 rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x100a); in _rtl92ee_hw_configure()
1002 rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x100a); in _rtl92ee_hw_configure()
1005 rtl_write_byte(rtlpriv, 0x4C7, 0x80); in _rtl92ee_hw_configure()
1007 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x20); in _rtl92ee_hw_configure()
1009 rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, 0x1717); in _rtl92ee_hw_configure()
1012 rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff); in _rtl92ee_hw_configure()
1013 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff); in _rtl92ee_hw_configure()
1018 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92ee_enable_aspm_back_door() local
1023 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0x78); in _rtl92ee_enable_aspm_back_door()
1024 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x2); in _rtl92ee_enable_aspm_back_door()
1025 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2); in _rtl92ee_enable_aspm_back_door()
1029 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2); in _rtl92ee_enable_aspm_back_door()
1034 tmp32 = rtl_read_dword(rtlpriv, REG_BACKDOOR_DBI_RDATA); in _rtl92ee_enable_aspm_back_door()
1037 rtl_write_dword(rtlpriv, REG_BACKDOOR_DBI_WDATA, in _rtl92ee_enable_aspm_back_door()
1039 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0xf078); in _rtl92ee_enable_aspm_back_door()
1040 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x1); in _rtl92ee_enable_aspm_back_door()
1042 tmp8 = rtl_read_byte(rtlpriv, in _rtl92ee_enable_aspm_back_door()
1047 tmp8 = rtl_read_byte(rtlpriv, in _rtl92ee_enable_aspm_back_door()
1054 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0x70c); in _rtl92ee_enable_aspm_back_door()
1055 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x2); in _rtl92ee_enable_aspm_back_door()
1056 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2); in _rtl92ee_enable_aspm_back_door()
1060 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2); in _rtl92ee_enable_aspm_back_door()
1064 tmp32 = rtl_read_dword(rtlpriv, REG_BACKDOOR_DBI_RDATA); in _rtl92ee_enable_aspm_back_door()
1065 rtl_write_dword(rtlpriv, REG_BACKDOOR_DBI_WDATA, in _rtl92ee_enable_aspm_back_door()
1067 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0xf70c); in _rtl92ee_enable_aspm_back_door()
1068 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x1); in _rtl92ee_enable_aspm_back_door()
1071 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2); in _rtl92ee_enable_aspm_back_door()
1075 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2); in _rtl92ee_enable_aspm_back_door()
1079 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0x718); in _rtl92ee_enable_aspm_back_door()
1080 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x2); in _rtl92ee_enable_aspm_back_door()
1081 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2); in _rtl92ee_enable_aspm_back_door()
1085 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2); in _rtl92ee_enable_aspm_back_door()
1089 tmp32 = rtl_read_dword(rtlpriv, REG_BACKDOOR_DBI_RDATA); in _rtl92ee_enable_aspm_back_door()
1090 rtl_write_dword(rtlpriv, REG_BACKDOOR_DBI_WDATA, in _rtl92ee_enable_aspm_back_door()
1092 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0xf718); in _rtl92ee_enable_aspm_back_door()
1093 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x1); in _rtl92ee_enable_aspm_back_door()
1095 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2); in _rtl92ee_enable_aspm_back_door()
1099 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2); in _rtl92ee_enable_aspm_back_door()
1106 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92ee_enable_hw_security_config() local
1110 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, in rtl92ee_enable_hw_security_config()
1112 rtlpriv->sec.pairwise_enc_algorithm, in rtl92ee_enable_hw_security_config()
1113 rtlpriv->sec.group_enc_algorithm); in rtl92ee_enable_hw_security_config()
1115 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { in rtl92ee_enable_hw_security_config()
1116 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, in rtl92ee_enable_hw_security_config()
1123 if (rtlpriv->sec.use_defaultkey) { in rtl92ee_enable_hw_security_config()
1130 tmp = rtl_read_byte(rtlpriv, REG_CR + 1); in rtl92ee_enable_hw_security_config()
1131 rtl_write_byte(rtlpriv, REG_CR + 1, tmp | BIT(1)); in rtl92ee_enable_hw_security_config()
1133 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, in rtl92ee_enable_hw_security_config()
1136 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value); in rtl92ee_enable_hw_security_config()
1139 static bool _rtl8192ee_check_pcie_dma_hang(struct rtl_priv *rtlpriv) in _rtl8192ee_check_pcie_dma_hang() argument
1144 tmp = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 3); in _rtl8192ee_check_pcie_dma_hang()
1146 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 3, in _rtl8192ee_check_pcie_dma_hang()
1154 tmp = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 3); in _rtl8192ee_check_pcie_dma_hang()
1156 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, in _rtl8192ee_check_pcie_dma_hang()
1163 static void _rtl8192ee_reset_pcie_interface_dma(struct rtl_priv *rtlpriv, in _rtl8192ee_reset_pcie_interface_dma() argument
1170 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, in _rtl8192ee_reset_pcie_interface_dma()
1181 tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL); in _rtl8192ee_reset_pcie_interface_dma()
1183 rtl_write_byte(rtlpriv, REG_RSV_CTRL, tmp); in _rtl8192ee_reset_pcie_interface_dma()
1184 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2); in _rtl8192ee_reset_pcie_interface_dma()
1186 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp); in _rtl8192ee_reset_pcie_interface_dma()
1192 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); in _rtl8192ee_reset_pcie_interface_dma()
1197 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2))); in _rtl8192ee_reset_pcie_interface_dma()
1201 backup_pcie_dma_pause = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 1); in _rtl8192ee_reset_pcie_interface_dma()
1203 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFF); in _rtl8192ee_reset_pcie_interface_dma()
1209 rtl_write_byte(rtlpriv, REG_CR, 0); in _rtl8192ee_reset_pcie_interface_dma()
1215 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); in _rtl8192ee_reset_pcie_interface_dma()
1217 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp); in _rtl8192ee_reset_pcie_interface_dma()
1222 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); in _rtl8192ee_reset_pcie_interface_dma()
1224 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp); in _rtl8192ee_reset_pcie_interface_dma()
1230 rtl_write_byte(rtlpriv, REG_CR, 0xFF); in _rtl8192ee_reset_pcie_interface_dma()
1241 tmp = rtl_read_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2); in _rtl8192ee_reset_pcie_interface_dma()
1243 rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2, tmp); in _rtl8192ee_reset_pcie_interface_dma()
1256 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL); in _rtl8192ee_reset_pcie_interface_dma()
1257 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, in _rtl8192ee_reset_pcie_interface_dma()
1260 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, in _rtl8192ee_reset_pcie_interface_dma()
1267 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2); in _rtl8192ee_reset_pcie_interface_dma()
1269 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp); in _rtl8192ee_reset_pcie_interface_dma()
1274 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92ee_hw_init() local
1277 struct rtl_phy *rtlphy = &rtlpriv->phy; in rtl92ee_hw_init()
1284 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, " Rtl8192EE hw init\n"); in rtl92ee_hw_init()
1285 rtlpriv->rtlhal.being_init_adapter = true; in rtl92ee_hw_init()
1286 rtlpriv->intf_ops->disable_aspm(hw); in rtl92ee_hw_init()
1288 tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CLKR+1); in rtl92ee_hw_init()
1289 u1byte = rtl_read_byte(rtlpriv, REG_CR); in rtl92ee_hw_init()
1297 if (_rtl8192ee_check_pcie_dma_hang(rtlpriv)) { in rtl92ee_hw_init()
1298 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "92ee dma hang!\n"); in rtl92ee_hw_init()
1299 _rtl8192ee_reset_pcie_interface_dma(rtlpriv, in rtl92ee_hw_init()
1306 rtl_write_byte(rtlpriv, 0x577, 0x03); in rtl92ee_hw_init()
1309 rtl_write_byte(rtlpriv, REG_AFE_CTRL4, 0x2A); in rtl92ee_hw_init()
1310 rtl_write_byte(rtlpriv, REG_AFE_CTRL4 + 1, 0x00); in rtl92ee_hw_init()
1311 rtl_write_byte(rtlpriv, REG_AFE_CTRL2, 0x83); in rtl92ee_hw_init()
1314 if (rtlpriv->btcoexist.btc_info.btcoexist == 1) { in rtl92ee_hw_init()
1315 rtl_write_byte(rtlpriv, 0x64, 0); in rtl92ee_hw_init()
1316 rtl_write_byte(rtlpriv, 0x65, 1); in rtl92ee_hw_init()
1324 rtl_write_word(rtlpriv, REG_PCIE_CTRL_REG, 0x8000); in rtl92ee_hw_init()
1327 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, in rtl92ee_hw_init()
1380 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr); in rtl92ee_hw_init()
1382 rtlpriv->intf_ops->enable_aspm(hw); in rtl92ee_hw_init()
1386 rtlpriv->rtlhal.being_init_adapter = false; in rtl92ee_hw_init()
1404 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "PA BIAS path A\n"); in rtl92ee_hw_init()
1409 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "PA BIAS path B\n"); in rtl92ee_hw_init()
1412 rtl_write_byte(rtlpriv, REG_NAV_UPPER, ((30000 + 127) / 128)); in rtl92ee_hw_init()
1415 tmp_u4b = rtl_read_dword(rtlpriv, REG_SYS_SWR_CTRL1); in rtl92ee_hw_init()
1416 rtl_write_byte(rtlpriv, REG_SYS_SWR_CTRL2, 0x75); in rtl92ee_hw_init()
1418 rtl_write_dword(rtlpriv, REG_SYS_SWR_CTRL1, tmp_u4b); in rtl92ee_hw_init()
1422 rtl_write_dword(rtlpriv, 0x4fc, 0); in rtl92ee_hw_init()
1424 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, in rtl92ee_hw_init()
1431 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92ee_read_chip_version() local
1432 struct rtl_phy *rtlphy = &rtlpriv->phy; in _rtl92ee_read_chip_version()
1438 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG1); in _rtl92ee_read_chip_version()
1444 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, in _rtl92ee_read_chip_version()
1454 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92ee_set_media_status() local
1455 u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc; in _rtl92ee_set_media_status()
1462 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, in _rtl92ee_set_media_status()
1468 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, in _rtl92ee_set_media_status()
1474 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, in _rtl92ee_set_media_status()
1480 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, in _rtl92ee_set_media_status()
1494 if (mode != MSR_AP && rtlpriv->mac80211.link_state < MAC80211_LINKED) { in _rtl92ee_set_media_status()
1506 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, in _rtl92ee_set_media_status()
1511 rtl_write_byte(rtlpriv, MSR, bt_msr | mode); in _rtl92ee_set_media_status()
1512 rtlpriv->cfg->ops->led_control(hw, ledaction); in _rtl92ee_set_media_status()
1514 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00); in _rtl92ee_set_media_status()
1516 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66); in _rtl92ee_set_media_status()
1522 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92ee_set_check_bssid() local
1526 if (rtlpriv->psc.rfpwr_state != ERFON) in rtl92ee_set_check_bssid()
1531 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, in rtl92ee_set_check_bssid()
1537 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, in rtl92ee_set_check_bssid()
1544 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92ee_set_network_type() local
1549 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) { in rtl92ee_set_network_type()
1563 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92ee_set_qos() local
1568 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f); in rtl92ee_set_qos()
1574 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322); in rtl92ee_set_qos()
1577 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222); in rtl92ee_set_qos()
1587 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92ee_enable_interrupt() local
1590 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF); in rtl92ee_enable_interrupt()
1591 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF); in rtl92ee_enable_interrupt()
1597 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92ee_disable_interrupt() local
1600 rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED); in rtl92ee_disable_interrupt()
1601 rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED); in rtl92ee_disable_interrupt()
1608 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92ee_poweroff_adapter() local
1614 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "POWER OFF adapter\n"); in _rtl92ee_poweroff_adapter()
1617 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, in _rtl92ee_poweroff_adapter()
1620 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); in _rtl92ee_poweroff_adapter()
1623 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->fw_ready) in _rtl92ee_poweroff_adapter()
1627 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); in _rtl92ee_poweroff_adapter()
1628 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2)))); in _rtl92ee_poweroff_adapter()
1631 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00); in _rtl92ee_poweroff_adapter()
1634 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, in _rtl92ee_poweroff_adapter()
1638 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1); in _rtl92ee_poweroff_adapter()
1639 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0)))); in _rtl92ee_poweroff_adapter()
1640 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1); in _rtl92ee_poweroff_adapter()
1641 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp | BIT(0))); in _rtl92ee_poweroff_adapter()
1644 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E); in _rtl92ee_poweroff_adapter()
1649 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92ee_card_disable() local
1654 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "RTL8192ee card disable\n"); in rtl92ee_card_disable()
1663 if (rtlpriv->rtlhal.driver_is_goingto_unload || in rtl92ee_card_disable()
1665 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF); in rtl92ee_card_disable()
1670 if (!rtlpriv->cfg->ops->get_btc_status()) in rtl92ee_card_disable()
1671 rtlpriv->phy.iqk_initialized = false; in rtl92ee_card_disable()
1677 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92ee_interrupt_recognized() local
1680 intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0]; in rtl92ee_interrupt_recognized()
1681 rtl_write_dword(rtlpriv, ISR, intvec->inta); in rtl92ee_interrupt_recognized()
1683 intvec->intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1]; in rtl92ee_interrupt_recognized()
1684 rtl_write_dword(rtlpriv, REG_HISRE, intvec->intb); in rtl92ee_interrupt_recognized()
1689 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92ee_set_beacon_related_registers() local
1697 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window); in rtl92ee_set_beacon_related_registers()
1698 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); in rtl92ee_set_beacon_related_registers()
1699 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f); in rtl92ee_set_beacon_related_registers()
1700 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18); in rtl92ee_set_beacon_related_registers()
1701 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18); in rtl92ee_set_beacon_related_registers()
1702 rtl_write_byte(rtlpriv, 0x606, 0x30); in rtl92ee_set_beacon_related_registers()
1704 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val); in rtl92ee_set_beacon_related_registers()
1709 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92ee_set_beacon_interval() local
1713 rtl_dbg(rtlpriv, COMP_BEACON, DBG_DMESG, in rtl92ee_set_beacon_interval()
1715 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval); in rtl92ee_set_beacon_interval()
1721 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92ee_update_interrupt_mask() local
1724 rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD, in rtl92ee_update_interrupt_mask()
1788 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl8192ee_read_power_value_fromprom() local
1791 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, in _rtl8192ee_read_power_value_fromprom()
1798 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, in _rtl8192ee_read_power_value_fromprom()
2016 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92ee_read_txpower_info_from_hwpg() local
2080 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, in _rtl92ee_read_txpower_info_from_hwpg()
2091 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, in _rtl92ee_read_txpower_info_from_hwpg()
2097 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92ee_read_adapter_info() local
2110 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params)) in _rtl92ee_read_adapter_info()
2116 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, in _rtl92ee_read_adapter_info()
2133 if (rtlpriv->btcoexist.btc_info.btcoexist == 1) in _rtl92ee_read_adapter_info()
2137 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, in _rtl92ee_read_adapter_info()
2170 struct rtl_priv *rtlpriv = rtl_priv(hw); in _rtl92ee_hal_customized_behavior() local
2173 rtlpriv->ledctl.led_opendrain = true; in _rtl92ee_hal_customized_behavior()
2175 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, in _rtl92ee_hal_customized_behavior()
2181 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92ee_read_eeprom_info() local
2183 struct rtl_phy *rtlphy = &rtlpriv->phy; in rtl92ee_read_eeprom_info()
2189 rtlpriv->dm.rfpath_rxenable[0] = true; in rtl92ee_read_eeprom_info()
2191 rtlpriv->dm.rfpath_rxenable[0] = true; in rtl92ee_read_eeprom_info()
2192 rtlpriv->dm.rfpath_rxenable[1] = true; in rtl92ee_read_eeprom_info()
2194 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n", in rtl92ee_read_eeprom_info()
2196 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR); in rtl92ee_read_eeprom_info()
2198 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n"); in rtl92ee_read_eeprom_info()
2201 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n"); in rtl92ee_read_eeprom_info()
2205 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); in rtl92ee_read_eeprom_info()
2253 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92ee_update_hal_rate_mask() local
2254 struct rtl_phy *rtlphy = &rtlpriv->phy; in rtl92ee_update_hal_rate_mask()
2364 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG, in rtl92ee_update_hal_rate_mask()
2375 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG, in rtl92ee_update_hal_rate_mask()
2388 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92ee_update_hal_rate_tbl() local
2390 if (rtlpriv->dm.useramask) in rtl92ee_update_hal_rate_tbl()
2396 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92ee_update_channel_access_setting() local
2400 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, in rtl92ee_update_channel_access_setting()
2406 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer); in rtl92ee_update_channel_access_setting()
2419 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92ee_set_key() local
2441 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n"); in rtl92ee_set_key()
2448 memset(rtlpriv->sec.key_buf[idx], 0, in rtl92ee_set_key()
2450 rtlpriv->sec.key_len[idx] = 0; in rtl92ee_set_key()
2469 rtl_dbg(rtlpriv, COMP_ERR, DBG_DMESG, in rtl92ee_set_key()
2475 if (is_wepkey || rtlpriv->sec.use_defaultkey) { in rtl92ee_set_key()
2500 if (rtlpriv->sec.key_len[key_index] == 0) { in rtl92ee_set_key()
2501 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, in rtl92ee_set_key()
2509 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, in rtl92ee_set_key()
2512 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, in rtl92ee_set_key()
2518 rtlpriv->sec.key_buf[key_index]); in rtl92ee_set_key()
2520 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, in rtl92ee_set_key()
2529 rtlpriv->sec.key_buf[entry_id]); in rtl92ee_set_key()
2535 rtlpriv->sec.key_buf[entry_id]); in rtl92ee_set_key()
2544 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92ee_read_bt_coexist_info_from_hwpg() local
2550 rtlpriv->btcoexist.btc_info.btcoexist = 1; in rtl92ee_read_bt_coexist_info_from_hwpg()
2552 rtlpriv->btcoexist.btc_info.btcoexist = 0; in rtl92ee_read_bt_coexist_info_from_hwpg()
2554 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8192E; in rtl92ee_read_bt_coexist_info_from_hwpg()
2555 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2; in rtl92ee_read_bt_coexist_info_from_hwpg()
2557 rtlpriv->btcoexist.btc_info.btcoexist = 1; in rtl92ee_read_bt_coexist_info_from_hwpg()
2558 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8192E; in rtl92ee_read_bt_coexist_info_from_hwpg()
2559 rtlpriv->btcoexist.btc_info.ant_num = ANT_X1; in rtl92ee_read_bt_coexist_info_from_hwpg()
2565 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92ee_bt_reg_init() local
2568 rtlpriv->btcoexist.reg_bt_iso = 2; in rtl92ee_bt_reg_init()
2570 rtlpriv->btcoexist.reg_bt_sco = 3; in rtl92ee_bt_reg_init()
2572 rtlpriv->btcoexist.reg_bt_sco = 0; in rtl92ee_bt_reg_init()
2577 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92ee_bt_hw_init() local
2579 if (rtlpriv->cfg->ops->get_btc_status()) in rtl92ee_bt_hw_init()
2580 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv); in rtl92ee_bt_hw_init()
2595 struct rtl_priv *rtlpriv = rtl_priv(hw); in rtl92ee_allow_all_destaddr() local
2604 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config); in rtl92ee_allow_all_destaddr()
2606 rtl_dbg(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD, in rtl92ee_allow_all_destaddr()