Lines Matching refs:path
94 u8 path; in _wait_rx_mode() local
98 for (path = 0; path < RF_PATH_MAX; path++) { in _wait_rx_mode()
99 if (!(kpath & BIT(path))) in _wait_rx_mode()
103 2, 5000, false, rtwdev, path, 0x00, in _wait_rx_mode()
107 path, ret); in _wait_rx_mode()
254 enum rtw89_rf_path path, u8 index) in _dack_reload_by_path() argument
266 if (path == RF_PATH_A) in _dack_reload_by_path()
275 tmp |= dack->msbk_d[path][index][i + 12] << (i * 8); in _dack_reload_by_path()
283 tmp |= dack->msbk_d[path][index][i + 8] << (i * 8); in _dack_reload_by_path()
291 tmp |= dack->msbk_d[path][index][i + 4] << (i * 8); in _dack_reload_by_path()
299 tmp |= dack->msbk_d[path][index][i] << (i * 8); in _dack_reload_by_path()
306 tmp = (dack->biask_d[path][index] << 22) | in _dack_reload_by_path()
307 (dack->dadck_d[path][index] << 14); in _dack_reload_by_path()
312 static void _dack_reload(struct rtw89_dev *rtwdev, enum rtw89_rf_path path) in _dack_reload() argument
317 _dack_reload_by_path(rtwdev, path, i); in _dack_reload()
319 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _dack_reload()
325 static void _check_addc(struct rtw89_dev *rtwdev, enum rtw89_rf_path path) in _check_addc() argument
331 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _check_addc()
345 "[DACK]S%d,dc_re = 0x%x,dc_im =0x%x\n", path, dc_re, dc_im); in _check_addc()
395 static void _check_dadc(struct rtw89_dev *rtwdev, enum rtw89_rf_path path) in _check_dadc() argument
397 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _check_dadc()
401 _check_addc(rtwdev, path); in _check_dadc()
403 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _check_dadc()
551 static void _iqk_read_fft_dbcc0(struct rtw89_dev *rtwdev, u8 path) in _iqk_read_fft_dbcc0() argument
571 path, i, fft[i]); in _iqk_read_fft_dbcc0()
574 static void _iqk_read_xym_dbcc0(struct rtw89_dev *rtwdev, u8 path) in _iqk_read_xym_dbcc0() argument
580 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, B_NCTL_CFG_SPAGE, path); in _iqk_read_xym_dbcc0()
586 tmp = rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD); in _iqk_read_xym_dbcc0()
588 path, BIT(path), tmp); in _iqk_read_xym_dbcc0()
592 rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD, 0x40000000); in _iqk_read_xym_dbcc0()
597 static void _iqk_read_txcfir_dbcc0(struct rtw89_dev *rtwdev, u8 path, in _iqk_read_txcfir_dbcc0() argument
608 if (path >= RTW8852A_IQK_SS) { in _iqk_read_txcfir_dbcc0()
609 rtw89_warn(rtwdev, "cfir path %d out of range\n", path); in _iqk_read_txcfir_dbcc0()
618 rtw89_phy_write32_mask(rtwdev, R_W_COEF + (path << 8), MASKDWORD, 0x00000001); in _iqk_read_txcfir_dbcc0()
620 base_addr = base_addrs[path][group]; in _iqk_read_txcfir_dbcc0()
629 if (path == 0x0) { in _iqk_read_txcfir_dbcc0()
650 rtw89_phy_write32_clr(rtwdev, R_W_COEF + (path << 8), MASKDWORD); in _iqk_read_txcfir_dbcc0()
651 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT + (path << 8), B_KIP_RPT_SEL, 0xc); in _iqk_read_txcfir_dbcc0()
653 tmp = rtw89_phy_read32_mask(rtwdev, R_RPT_PER + (path << 8), MASKDWORD); in _iqk_read_txcfir_dbcc0()
654 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8%lxfc = %x\n", path, in _iqk_read_txcfir_dbcc0()
655 BIT(path), tmp); in _iqk_read_txcfir_dbcc0()
658 static void _iqk_read_rxcfir_dbcc0(struct rtw89_dev *rtwdev, u8 path, in _iqk_read_rxcfir_dbcc0() argument
669 if (path >= RTW8852A_IQK_SS) { in _iqk_read_rxcfir_dbcc0()
670 rtw89_warn(rtwdev, "cfir path %d out of range\n", path); in _iqk_read_rxcfir_dbcc0()
679 rtw89_phy_write32_mask(rtwdev, R_W_COEF + (path << 8), MASKDWORD, 0x00000001); in _iqk_read_rxcfir_dbcc0()
681 base_addr = base_addrs[path][group]; in _iqk_read_rxcfir_dbcc0()
689 if (path == 0x0) { in _iqk_read_rxcfir_dbcc0()
710 rtw89_phy_write32_clr(rtwdev, R_W_COEF + (path << 8), MASKDWORD); in _iqk_read_rxcfir_dbcc0()
711 rtw89_phy_write32_mask(rtwdev, R_KIP_RPT + (path << 8), B_KIP_RPT_SEL, 0xd); in _iqk_read_rxcfir_dbcc0()
712 tmp = rtw89_phy_read32_mask(rtwdev, R_RPT_PER + (path << 8), MASKDWORD); in _iqk_read_rxcfir_dbcc0()
713 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8%lxfc = %x\n", path, in _iqk_read_rxcfir_dbcc0()
714 BIT(path), tmp); in _iqk_read_rxcfir_dbcc0()
717 static void _iqk_sram(struct rtw89_dev *rtwdev, u8 path) in _iqk_sram() argument
743 static void _iqk_rxk_setting(struct rtw89_dev *rtwdev, u8 path) in _iqk_rxk_setting() argument
748 rtw89_phy_write32_set(rtwdev, R_P0_NRBW + (path << 13), B_P0_NRBW_DBG); in _iqk_rxk_setting()
761 switch (iqk_info->iqk_band[path]) { in _iqk_rxk_setting()
763 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RXK2); in _iqk_rxk_setting()
764 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL2G, 0x1); in _iqk_rxk_setting()
767 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RXK2); in _iqk_rxk_setting()
768 rtw89_write_rf(rtwdev, path, RR_WLSEL, RR_WLSEL_AG, 0x5); in _iqk_rxk_setting()
769 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x1); in _iqk_rxk_setting()
774 tmp = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); in _iqk_rxk_setting()
775 rtw89_write_rf(rtwdev, path, RR_RSV4, RFREG_MASK, tmp); in _iqk_rxk_setting()
776 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_OFF, 0x13); in _iqk_rxk_setting()
777 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0); in _iqk_rxk_setting()
778 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x1); in _iqk_rxk_setting()
782 static bool _iqk_check_cal(struct rtw89_dev *rtwdev, u8 path, u8 ktype) in _iqk_check_cal() argument
793 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, ret=%d\n", path, ret); in _iqk_check_cal()
796 "[IQK]S%x, type= %x, 0x8008 = 0x%x\n", path, ktype, tmp); in _iqk_check_cal()
802 enum rtw89_phy_idx phy_idx, u8 path, u8 ktype) in _iqk_one_shot() argument
807 u8 phy_map = rtw89_btc_path_phymap(rtwdev, phy_idx, path); in _iqk_one_shot()
810 if (path == RF_PATH_A) in _iqk_one_shot()
818 iqk_cmd = 0x008 | (1 << (4 + path)) | (path << 1); in _iqk_one_shot()
823 iqk_cmd = 0x108 | (1 << (4 + path)); in _iqk_one_shot()
828 iqk_cmd = 0x208 | (1 << (4 + path)); in _iqk_one_shot()
833 iqk_cmd = 0x008 | (1 << (path + 4)) | in _iqk_one_shot()
834 (((0x8 + iqk_info->iqk_bw[path]) & 0xf) << 8); in _iqk_one_shot()
837 iqk_cmd = 0x508 | (1 << (4 + path)) | (path << 1); in _iqk_one_shot()
842 iqk_cmd = 0x008 | (1 << (path + 4)) | in _iqk_one_shot()
843 (((0xb + iqk_info->iqk_bw[path]) & 0xf) << 8); in _iqk_one_shot()
848 iqk_cmd = 0x308 | (1 << (4 + path)); in _iqk_one_shot()
853 iqk_cmd = 0x608 | (1 << (4 + path)); in _iqk_one_shot()
862 fail = _iqk_check_cal(rtwdev, path, ktype); in _iqk_one_shot()
864 _iqk_read_xym_dbcc0(rtwdev, path); in _iqk_one_shot()
866 _iqk_read_fft_dbcc0(rtwdev, path); in _iqk_one_shot()
868 _iqk_sram(rtwdev, path); in _iqk_one_shot()
871 _iqk_read_txcfir_dbcc0(rtwdev, path, 0x0); in _iqk_one_shot()
872 _iqk_read_txcfir_dbcc0(rtwdev, path, 0x1); in _iqk_one_shot()
873 _iqk_read_txcfir_dbcc0(rtwdev, path, 0x2); in _iqk_one_shot()
874 _iqk_read_txcfir_dbcc0(rtwdev, path, 0x3); in _iqk_one_shot()
876 _iqk_read_rxcfir_dbcc0(rtwdev, path, 0x0); in _iqk_one_shot()
877 _iqk_read_rxcfir_dbcc0(rtwdev, path, 0x1); in _iqk_one_shot()
878 _iqk_read_rxcfir_dbcc0(rtwdev, path, 0x2); in _iqk_one_shot()
879 _iqk_read_rxcfir_dbcc0(rtwdev, path, 0x3); in _iqk_one_shot()
891 enum rtw89_phy_idx phy_idx, u8 path) in _rxk_group_sel() argument
905 switch (iqk_info->iqk_band[path]) { in _rxk_group_sel()
907 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG, rxgn_g[gp]); in _rxk_group_sel()
908 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C2G, attc2_g[gp]); in _rxk_group_sel()
909 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C1G, attc1_g[gp]); in _rxk_group_sel()
912 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG, rxgn_a[gp]); in _rxk_group_sel()
913 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_C2, attc2_a[gp]); in _rxk_group_sel()
914 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_C1, attc1_a[gp]); in _rxk_group_sel()
920 rf0 = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK); in _rxk_group_sel()
924 rtw89_phy_write32_clr(rtwdev, R_IQK_RES + (path << 8), B_IQK_RES_RXCFIR); in _rxk_group_sel()
925 rtw89_phy_write32_set(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL); in _rxk_group_sel()
926 rtw89_phy_write32_clr(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3); in _rxk_group_sel()
927 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_GP, gp); in _rxk_group_sel()
930 fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_RXK); in _rxk_group_sel()
931 rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(16 + gp + path * 4), fail); in _rxk_group_sel()
934 switch (iqk_info->iqk_band[path]) { in _rxk_group_sel()
936 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL2G, 0x0); in _rxk_group_sel()
937 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0); in _rxk_group_sel()
940 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x0); in _rxk_group_sel()
941 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0); in _rxk_group_sel()
942 rtw89_write_rf(rtwdev, path, RR_WLSEL, RR_WLSEL_AG, 0x0); in _rxk_group_sel()
947 iqk_info->nb_rxcfir[path] = 0x40000000; in _rxk_group_sel()
948 rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8), in _rxk_group_sel()
950 iqk_info->is_wb_rxiqk[path] = true; in _rxk_group_sel()
955 enum rtw89_phy_idx phy_idx, u8 path) in _iqk_nbrxk() argument
968 switch (iqk_info->iqk_band[path]) { in _iqk_nbrxk()
970 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG, idxrxgain_g); in _iqk_nbrxk()
971 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C2G, idxattc2_g); in _iqk_nbrxk()
972 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_C1G, idxattc1_g); in _iqk_nbrxk()
975 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXG, idxrxgain_a); in _iqk_nbrxk()
976 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_C2, idxattc2_a); in _iqk_nbrxk()
977 rtw89_write_rf(rtwdev, path, RR_RXA2, RR_RXA2_C1, idxattc1_a); in _iqk_nbrxk()
983 rf0 = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK); in _iqk_nbrxk()
987 rtw89_phy_write32_clr(rtwdev, R_IQK_RES + (path << 8), B_IQK_RES_RXCFIR); in _iqk_nbrxk()
988 rtw89_phy_write32_set(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL); in _iqk_nbrxk()
989 rtw89_phy_write32_clr(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3); in _iqk_nbrxk()
990 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), in _iqk_nbrxk()
994 fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBRXK); in _iqk_nbrxk()
996 switch (iqk_info->iqk_band[path]) { in _iqk_nbrxk()
998 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL2G, 0x0); in _iqk_nbrxk()
999 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0); in _iqk_nbrxk()
1002 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_SEL5G, 0x0); in _iqk_nbrxk()
1003 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0); in _iqk_nbrxk()
1004 rtw89_write_rf(rtwdev, path, RR_WLSEL, RR_WLSEL_AG, 0x0); in _iqk_nbrxk()
1010 tmp = rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD); in _iqk_nbrxk()
1011 iqk_info->nb_rxcfir[path] = tmp | 0x2; in _iqk_nbrxk()
1013 iqk_info->nb_rxcfir[path] = 0x40000002; in _iqk_nbrxk()
1018 static void _iqk_rxclk_setting(struct rtw89_dev *rtwdev, u8 path) in _iqk_rxclk_setting() argument
1022 if (iqk_info->iqk_bw[path] == RTW89_CHANNEL_WIDTH_80) { in _iqk_rxclk_setting()
1024 rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), in _iqk_rxclk_setting()
1026 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK + (path << 13), in _iqk_rxclk_setting()
1028 rtw89_phy_write32_set(rtwdev, R_P0_RXCK + (path << 13), B_P0_RXCK_ON); in _iqk_rxclk_setting()
1032 rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), in _iqk_rxclk_setting()
1034 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK + (path << 13), in _iqk_rxclk_setting()
1036 rtw89_phy_write32_set(rtwdev, R_P0_RXCK + (path << 13), B_P0_RXCK_ON); in _iqk_rxclk_setting()
1043 enum rtw89_phy_idx phy_idx, u8 path) in _txk_group_sel() argument
1056 switch (iqk_info->iqk_band[path]) { in _txk_group_sel()
1058 rtw89_phy_write32_mask(rtwdev, R_RFGAIN_BND + (path << 8), in _txk_group_sel()
1060 rtw89_write_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_ALL, in _txk_group_sel()
1062 rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT1, in _txk_group_sel()
1064 rtw89_write_rf(rtwdev, path, RR_TXG2, RR_TXG2_ATT0, in _txk_group_sel()
1066 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), in _txk_group_sel()
1070 rtw89_phy_write32_mask(rtwdev, R_RFGAIN_BND + (path << 8), in _txk_group_sel()
1072 rtw89_write_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_ALL, in _txk_group_sel()
1074 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), in _txk_group_sel()
1080 rtw89_phy_write32_clr(rtwdev, R_IQK_RES + (path << 8), B_IQK_RES_TXCFIR); in _txk_group_sel()
1081 rtw89_phy_write32_set(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL); in _txk_group_sel()
1082 rtw89_phy_write32_set(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3); in _txk_group_sel()
1083 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), in _txk_group_sel()
1086 fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_TXK); in _txk_group_sel()
1087 rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(8 + gp + path * 4), fail); in _txk_group_sel()
1090 iqk_info->nb_txcfir[path] = 0x40000000; in _txk_group_sel()
1091 rtw89_phy_write32_mask(rtwdev, R_IQK_RES + (path << 8), in _txk_group_sel()
1093 iqk_info->is_wb_txiqk[path] = true; in _txk_group_sel()
1094 tmp = rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD); in _txk_group_sel()
1095 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8%lx38 = 0x%x\n", path, in _txk_group_sel()
1096 BIT(path), tmp); in _txk_group_sel()
1101 enum rtw89_phy_idx phy_idx, u8 path) in _iqk_nbtxk() argument
1112 switch (iqk_info->iqk_band[path]) { in _iqk_nbtxk()
1114 rtw89_phy_write32_mask(rtwdev, R_RFGAIN_BND + (path << 8), in _iqk_nbtxk()
1116 rtw89_write_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_ALL, g_mode_txgain); in _iqk_nbtxk()
1117 rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT1, attsmxr); in _iqk_nbtxk()
1118 rtw89_write_rf(rtwdev, path, RR_TXG2, RR_TXG2_ATT0, attsmxr); in _iqk_nbtxk()
1121 rtw89_phy_write32_mask(rtwdev, R_RFGAIN_BND + (path << 8), in _iqk_nbtxk()
1123 rtw89_write_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_ALL, a_mode_txgain); in _iqk_nbtxk()
1128 rtw89_phy_write32_clr(rtwdev, R_IQK_RES + (path << 8), B_IQK_RES_TXCFIR); in _iqk_nbtxk()
1129 rtw89_phy_write32_set(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL); in _iqk_nbtxk()
1130 rtw89_phy_write32_set(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3); in _iqk_nbtxk()
1131 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_GP, group); in _iqk_nbtxk()
1132 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, itqt); in _iqk_nbtxk()
1134 fail = _iqk_one_shot(rtwdev, phy_idx, path, ID_NBTXK); in _iqk_nbtxk()
1136 tmp = rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD); in _iqk_nbtxk()
1137 iqk_info->nb_txcfir[path] = tmp | 0x2; in _iqk_nbtxk()
1139 iqk_info->nb_txcfir[path] = 0x40000002; in _iqk_nbtxk()
1141 tmp = rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD); in _iqk_nbtxk()
1142 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, 0x8%lx38 = 0x%x\n", path, in _iqk_nbtxk()
1143 BIT(path), tmp); in _iqk_nbtxk()
1147 static void _lok_res_table(struct rtw89_dev *rtwdev, u8 path, u8 ibias) in _lok_res_table() argument
1151 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, ibias = %x\n", path, ibias); in _lok_res_table()
1152 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x2); in _lok_res_table()
1153 if (iqk_info->iqk_band[path] == RTW89_BAND_2G) in _lok_res_table()
1154 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, 0x0); in _lok_res_table()
1156 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, 0x1); in _lok_res_table()
1157 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, ibias); in _lok_res_table()
1158 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0); in _lok_res_table()
1161 static bool _lok_finetune_check(struct rtw89_dev *rtwdev, u8 path) in _lok_finetune_check() argument
1168 tmp = rtw89_read_rf(rtwdev, path, RR_TXMO, RFREG_MASK); in _lok_finetune_check()
1170 path, tmp); in _lok_finetune_check()
1173 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, i = 0x%x\n", path, core_i); in _lok_finetune_check()
1174 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%x, q = 0x%x\n", path, core_q); in _lok_finetune_check()
1182 enum rtw89_phy_idx phy_idx, u8 path) in _iqk_lok() argument
1190 switch (iqk_info->iqk_band[path]) { in _iqk_lok()
1192 rtw89_write_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_ALL, 0xe5e0); in _iqk_lok()
1196 rtw89_write_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_ALL, 0xe4e0); in _iqk_lok()
1203 rf0 = rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK); in _iqk_lok()
1206 rtw89_phy_write32_clr(rtwdev, R_IQK_RES + (path << 8), B_IQK_RES_TXCFIR); in _iqk_lok()
1207 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL, 0x1); in _iqk_lok()
1208 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_G3, 0x1); in _iqk_lok()
1209 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_GP, 0x0); in _iqk_lok()
1212 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, itqt); in _iqk_lok()
1213 tmp = _iqk_one_shot(rtwdev, phy_idx, path, ID_FLOK_COARSE); in _iqk_lok()
1214 iqk_info->lok_cor_fail[0][path] = tmp; in _iqk_lok()
1216 rtw89_phy_write32_mask(rtwdev, R_KIP_IQP + (path << 8), MASKDWORD, itqt); in _iqk_lok()
1217 tmp = _iqk_one_shot(rtwdev, phy_idx, path, ID_FLOK_FINE); in _iqk_lok()
1218 iqk_info->lok_fin_fail[0][path] = tmp; in _iqk_lok()
1219 fail = _lok_finetune_check(rtwdev, path); in _iqk_lok()
1223 static void _iqk_txk_setting(struct rtw89_dev *rtwdev, u8 path) in _iqk_txk_setting() argument
1227 rtw89_phy_write32_set(rtwdev, R_P0_NRBW + (path << 13), B_P0_NRBW_DBG); in _iqk_txk_setting()
1237 switch (iqk_info->iqk_band[path]) { in _iqk_txk_setting()
1239 rtw89_write_rf(rtwdev, path, RR_XALNA2, RR_XALNA2_SW, 0x00); in _iqk_txk_setting()
1240 rtw89_write_rf(rtwdev, path, RR_RCKD, RR_RCKD_POW, 0x3f); in _iqk_txk_setting()
1241 rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT2, 0x0); in _iqk_txk_setting()
1242 rtw89_write_rf(rtwdev, path, RR_TXG1, RR_TXG1_ATT1, 0x1); in _iqk_txk_setting()
1243 rtw89_write_rf(rtwdev, path, RR_TXG2, RR_TXG2_ATT0, 0x1); in _iqk_txk_setting()
1244 rtw89_write_rf(rtwdev, path, RR_TXGA, RR_TXGA_LOK_EN, 0x0); in _iqk_txk_setting()
1245 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x1); in _iqk_txk_setting()
1246 rtw89_write_rf(rtwdev, path, RR_LUTDBG, RR_LUTDBG_LOK, 0x0); in _iqk_txk_setting()
1247 rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_MASK, 0x000); in _iqk_txk_setting()
1248 rtw89_write_rf(rtwdev, path, RR_RSV2, RFREG_MASK, 0x80200); in _iqk_txk_setting()
1249 rtw89_write_rf(rtwdev, path, RR_DTXLOK, RFREG_MASK, 0x80200); in _iqk_txk_setting()
1250 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK, in _iqk_txk_setting()
1255 rtw89_write_rf(rtwdev, path, RR_XGLNA2, RR_XGLNA2_SW, 0x00); in _iqk_txk_setting()
1256 rtw89_write_rf(rtwdev, path, RR_RCKD, RR_RCKD_POW, 0x3f); in _iqk_txk_setting()
1257 rtw89_write_rf(rtwdev, path, RR_BIASA, RR_BIASA_A, 0x7); in _iqk_txk_setting()
1258 rtw89_write_rf(rtwdev, path, RR_TXGA, RR_TXGA_LOK_EN, 0x0); in _iqk_txk_setting()
1259 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x1); in _iqk_txk_setting()
1260 rtw89_write_rf(rtwdev, path, RR_LUTDBG, RR_LUTDBG_LOK, 0x0); in _iqk_txk_setting()
1261 rtw89_write_rf(rtwdev, path, RR_LUTWA, RR_LUTWA_MASK, 0x100); in _iqk_txk_setting()
1262 rtw89_write_rf(rtwdev, path, RR_RSV2, RFREG_MASK, 0x80200); in _iqk_txk_setting()
1263 rtw89_write_rf(rtwdev, path, RR_DTXLOK, RFREG_MASK, 0x80200); in _iqk_txk_setting()
1264 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, 0x1); in _iqk_txk_setting()
1265 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, 0x0); in _iqk_txk_setting()
1266 rtw89_write_rf(rtwdev, path, RR_MOD, RFREG_MASK, in _iqk_txk_setting()
1275 static void _iqk_txclk_setting(struct rtw89_dev *rtwdev, u8 path) in _iqk_txclk_setting() argument
1277 rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), MASKDWORD, 0xce000a08); in _iqk_txclk_setting()
1281 u8 path) in _iqk_info_iqk() argument
1287 iqk_info->thermal[path] = in _iqk_info_iqk()
1288 ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]); in _iqk_info_iqk()
1290 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_thermal = %d\n", path, in _iqk_info_iqk()
1291 iqk_info->thermal[path]); in _iqk_info_iqk()
1292 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_LOK_COR_fail= %d\n", path, in _iqk_info_iqk()
1293 iqk_info->lok_cor_fail[0][path]); in _iqk_info_iqk()
1294 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_LOK_FIN_fail= %d\n", path, in _iqk_info_iqk()
1295 iqk_info->lok_fin_fail[0][path]); in _iqk_info_iqk()
1296 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_TXIQK_fail = %d\n", path, in _iqk_info_iqk()
1297 iqk_info->iqk_tx_fail[0][path]); in _iqk_info_iqk()
1298 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK]S%d_RXIQK_fail= %d,\n", path, in _iqk_info_iqk()
1299 iqk_info->iqk_rx_fail[0][path]); in _iqk_info_iqk()
1300 flag = iqk_info->lok_cor_fail[0][path]; in _iqk_info_iqk()
1301 rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(0) << (path * 4), flag); in _iqk_info_iqk()
1302 flag = iqk_info->lok_fin_fail[0][path]; in _iqk_info_iqk()
1303 rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(1) << (path * 4), flag); in _iqk_info_iqk()
1304 flag = iqk_info->iqk_tx_fail[0][path]; in _iqk_info_iqk()
1305 rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(2) << (path * 4), flag); in _iqk_info_iqk()
1306 flag = iqk_info->iqk_rx_fail[0][path]; in _iqk_info_iqk()
1307 rtw89_phy_write32_mask(rtwdev, R_IQKINF, BIT(3) << (path * 4), flag); in _iqk_info_iqk()
1309 tmp = rtw89_phy_read32_mask(rtwdev, R_IQK_RES + (path << 8), MASKDWORD); in _iqk_info_iqk()
1310 iqk_info->bp_iqkenable[path] = tmp; in _iqk_info_iqk()
1311 tmp = rtw89_phy_read32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD); in _iqk_info_iqk()
1312 iqk_info->bp_txkresult[path] = tmp; in _iqk_info_iqk()
1313 tmp = rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD); in _iqk_info_iqk()
1314 iqk_info->bp_rxkresult[path] = tmp; in _iqk_info_iqk()
1319 tmp = rtw89_phy_read32_mask(rtwdev, R_IQKINF, 0x0000000f << (path * 4)); in _iqk_info_iqk()
1322 rtw89_phy_write32_mask(rtwdev, R_IQKINF2, 0x00ff0000 << (path * 4), in _iqk_info_iqk()
1327 void _iqk_by_path(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u8 path) in _iqk_by_path() argument
1334 _iqk_txclk_setting(rtwdev, path); in _iqk_by_path()
1337 _lok_res_table(rtwdev, path, ibias++); in _iqk_by_path()
1338 _iqk_txk_setting(rtwdev, path); in _iqk_by_path()
1339 lok_is_fail = _iqk_lok(rtwdev, phy_idx, path); in _iqk_by_path()
1344 iqk_info->iqk_tx_fail[0][path] = _iqk_nbtxk(rtwdev, phy_idx, path); in _iqk_by_path()
1346 iqk_info->iqk_tx_fail[0][path] = _txk_group_sel(rtwdev, phy_idx, path); in _iqk_by_path()
1348 _iqk_rxclk_setting(rtwdev, path); in _iqk_by_path()
1349 _iqk_rxk_setting(rtwdev, path); in _iqk_by_path()
1350 if (iqk_info->is_nbiqk || rtwdev->dbcc_en || iqk_info->iqk_band[path] == RTW89_BAND_2G) in _iqk_by_path()
1351 iqk_info->iqk_rx_fail[0][path] = _iqk_nbrxk(rtwdev, phy_idx, path); in _iqk_by_path()
1353 iqk_info->iqk_rx_fail[0][path] = _rxk_group_sel(rtwdev, phy_idx, path); in _iqk_by_path()
1355 _iqk_info_iqk(rtwdev, phy_idx, path); in _iqk_by_path()
1359 enum rtw89_phy_idx phy, u8 path) in _iqk_get_ch_info() argument
1369 if (iqk_info->iqk_mcc_ch[idx][path] == 0) { in _iqk_get_ch_info()
1375 idx = iqk_info->iqk_table_idx[path] + 1; in _iqk_get_ch_info()
1379 reg_rf18 = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); in _iqk_get_ch_info()
1383 iqk_info->iqk_band[path] = chan->band_type; in _iqk_get_ch_info()
1384 iqk_info->iqk_bw[path] = chan->band_width; in _iqk_get_ch_info()
1385 iqk_info->iqk_ch[path] = chan->channel; in _iqk_get_ch_info()
1388 "[IQK]iqk_info->iqk_band[%x] = 0x%x\n", path, in _iqk_get_ch_info()
1389 iqk_info->iqk_band[path]); in _iqk_get_ch_info()
1391 path, iqk_info->iqk_bw[path]); in _iqk_get_ch_info()
1393 path, iqk_info->iqk_ch[path]); in _iqk_get_ch_info()
1395 "[IQK]S%d (PHY%d): / DBCC %s/ %s/ CH%d/ %s\n", path, phy, in _iqk_get_ch_info()
1397 iqk_info->iqk_band[path] == 0 ? "2G" : in _iqk_get_ch_info()
1398 iqk_info->iqk_band[path] == 1 ? "5G" : "6G", in _iqk_get_ch_info()
1399 iqk_info->iqk_ch[path], in _iqk_get_ch_info()
1400 iqk_info->iqk_bw[path] == 0 ? "20M" : in _iqk_get_ch_info()
1401 iqk_info->iqk_bw[path] == 1 ? "40M" : "80M"); in _iqk_get_ch_info()
1408 rtw89_phy_write32_mask(rtwdev, R_IQKCH, 0x000f << (path * 16), in _iqk_get_ch_info()
1409 (u8)iqk_info->iqk_band[path]); in _iqk_get_ch_info()
1410 rtw89_phy_write32_mask(rtwdev, R_IQKCH, 0x00f0 << (path * 16), in _iqk_get_ch_info()
1411 (u8)iqk_info->iqk_bw[path]); in _iqk_get_ch_info()
1412 rtw89_phy_write32_mask(rtwdev, R_IQKCH, 0xff00 << (path * 16), in _iqk_get_ch_info()
1413 (u8)iqk_info->iqk_ch[path]); in _iqk_get_ch_info()
1419 u8 path) in _iqk_start_iqk() argument
1421 _iqk_by_path(rtwdev, phy_idx, path); in _iqk_start_iqk()
1424 static void _iqk_restore(struct rtw89_dev *rtwdev, u8 path) in _iqk_restore() argument
1428 rtw89_phy_write32_mask(rtwdev, R_TXIQC + (path << 8), MASKDWORD, in _iqk_restore()
1429 iqk_info->nb_txcfir[path]); in _iqk_restore()
1430 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), MASKDWORD, in _iqk_restore()
1431 iqk_info->nb_rxcfir[path]); in _iqk_restore()
1437 rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), MASKDWORD, 0x10010000); in _iqk_restore()
1438 rtw89_phy_write32_clr(rtwdev, R_KIP + (path << 8), B_KIP_RFGAIN); in _iqk_restore()
1439 rtw89_phy_write32_mask(rtwdev, R_CFIR_MAP + (path << 8), MASKDWORD, 0xe4e4e4e4); in _iqk_restore()
1440 rtw89_phy_write32_clr(rtwdev, R_CFIR_LUT + (path << 8), B_CFIR_LUT_SEL); in _iqk_restore()
1441 rtw89_phy_write32_clr(rtwdev, R_KIP_IQP + (path << 8), B_KIP_IQP_IQSW); in _iqk_restore()
1442 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), MASKDWORD, 0x00000002); in _iqk_restore()
1443 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x0); in _iqk_restore()
1444 rtw89_write_rf(rtwdev, path, RR_RCKD, RR_RCKD_POW, 0x0); in _iqk_restore()
1445 rtw89_write_rf(rtwdev, path, RR_LUTWE, RR_LUTWE_LOK, 0x0); in _iqk_restore()
1446 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX); in _iqk_restore()
1447 rtw89_write_rf(rtwdev, path, RR_TXRSV, RR_TXRSV_GAPK, 0x0); in _iqk_restore()
1448 rtw89_write_rf(rtwdev, path, RR_BIAS, RR_BIAS_GAPK, 0x0); in _iqk_restore()
1449 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x1); in _iqk_restore()
1453 enum rtw89_phy_idx phy_idx, u8 path) in _iqk_afebb_restore() argument
1472 static void _iqk_preset(struct rtw89_dev *rtwdev, u8 path) in _iqk_preset() argument
1475 u8 idx = iqk_info->iqk_table_idx[path]; in _iqk_preset()
1478 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8), in _iqk_preset()
1479 B_COEF_SEL_IQC, path & 0x1); in _iqk_preset()
1480 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), in _iqk_preset()
1481 B_CFIR_LUT_G2, path & 0x1); in _iqk_preset()
1483 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8), in _iqk_preset()
1485 rtw89_phy_write32_mask(rtwdev, R_CFIR_LUT + (path << 8), in _iqk_preset()
1488 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0); in _iqk_preset()
1494 rtw89_phy_write32_clr(rtwdev, R_LOAD_COEF + (path << 8), MASKDWORD); in _iqk_preset()
1498 enum rtw89_phy_idx phy_idx, u8 path) in _iqk_macbb_setting() argument
1519 static void _iqk_dbcc(struct rtw89_dev *rtwdev, u8 path) in _iqk_dbcc() argument
1526 if (path == 0x0) in _iqk_dbcc()
1531 _iqk_get_ch_info(rtwdev, phy_idx, path); in _iqk_dbcc()
1532 _iqk_macbb_setting(rtwdev, phy_idx, path); in _iqk_dbcc()
1533 _iqk_preset(rtwdev, path); in _iqk_dbcc()
1534 _iqk_start_iqk(rtwdev, phy_idx, path); in _iqk_dbcc()
1535 _iqk_restore(rtwdev, path); in _iqk_dbcc()
1536 _iqk_afebb_restore(rtwdev, phy_idx, path); in _iqk_dbcc()
1542 u8 path = 0x0; in _iqk_track() local
1551 for (path = 0; path < 1; path++) { in _iqk_track()
1552 cur_ther = ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]); in _iqk_track()
1554 if (abs(cur_ther - iqk->thermal[path]) > RTW8852A_IQK_THR_REK) in _iqk_track()
1561 static void _rck(struct rtw89_dev *rtwdev, enum rtw89_rf_path path) in _rck() argument
1567 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[RCK] ====== S%d RCK ======\n", path); in _rck()
1569 rf_reg5 = rtw89_read_rf(rtwdev, path, RR_RSV1, RFREG_MASK); in _rck()
1571 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0); in _rck()
1572 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX); in _rck()
1575 rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK)); in _rck()
1578 rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, 0x00240); in _rck()
1581 false, rtwdev, path, 0x1c, BIT(3)); in _rck()
1585 rck_val = rtw89_read_rf(rtwdev, path, RR_RCKC, RR_RCKC_CA); in _rck()
1586 rtw89_write_rf(rtwdev, path, RR_RCKC, RFREG_MASK, rck_val); in _rck()
1589 rtw89_write_rf(rtwdev, path, RR_RCKO, RR_RCKO_OFF, 0x4); in _rck()
1591 rtw89_write_rf(rtwdev, path, RR_RFC, RR_RFC_CKEN, 0x1); in _rck()
1592 rtw89_write_rf(rtwdev, path, RR_RFC, RR_RFC_CKEN, 0x0); in _rck()
1594 rtw89_write_rf(rtwdev, path, RR_RSV1, RFREG_MASK, rf_reg5); in _rck()
1598 rtw89_read_rf(rtwdev, path, RR_RCKC, RFREG_MASK), in _rck()
1599 rtw89_read_rf(rtwdev, path, RR_RCKS, RFREG_MASK), in _rck()
1600 rtw89_read_rf(rtwdev, path, RR_RCKO, RFREG_MASK)); in _rck()
1606 u8 ch, path; in _iqk_init() local
1624 for (path = 0; path < RTW8852A_IQK_SS; path++) { in _iqk_init()
1625 iqk_info->lok_cor_fail[ch][path] = false; in _iqk_init()
1626 iqk_info->lok_fin_fail[ch][path] = false; in _iqk_init()
1627 iqk_info->iqk_tx_fail[ch][path] = false; in _iqk_init()
1628 iqk_info->iqk_rx_fail[ch][path] = false; in _iqk_init()
1629 iqk_info->iqk_mcc_ch[ch][path] = 0x0; in _iqk_init()
1630 iqk_info->iqk_table_idx[path] = 0x0; in _iqk_init()
1636 enum rtw89_phy_idx phy_idx, u8 path) in _doiqk() argument
1652 _iqk_get_ch_info(rtwdev, phy_idx, path); in _doiqk()
1654 _rfk_backup_rf_reg(rtwdev, &backup_rf_val[path][0], path); in _doiqk()
1655 _iqk_macbb_setting(rtwdev, phy_idx, path); in _doiqk()
1656 _iqk_preset(rtwdev, path); in _doiqk()
1657 _iqk_start_iqk(rtwdev, phy_idx, path); in _doiqk()
1658 _iqk_restore(rtwdev, path); in _doiqk()
1659 _iqk_afebb_restore(rtwdev, phy_idx, path); in _doiqk()
1661 _rfk_restore_rf_reg(rtwdev, &backup_rf_val[path][0], path); in _doiqk()
1686 enum rtw89_rf_path path, bool is_afe) in _set_rx_dck() argument
1688 u8 phy_map = rtw89_btc_path_phymap(rtwdev, phy, path); in _set_rx_dck()
1693 path, is_afe ? "AFE" : "RFC"); in _set_rx_dck()
1695 ori_val = rtw89_phy_read32_mask(rtwdev, R_P0_RXCK + (path << 13), MASKDWORD); in _set_rx_dck()
1698 rtw89_phy_write32_set(rtwdev, R_P0_NRBW + (path << 13), B_P0_NRBW_DBG); in _set_rx_dck()
1699 rtw89_phy_write32_set(rtwdev, R_P0_RXCK + (path << 13), B_P0_RXCK_ON); in _set_rx_dck()
1700 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK + (path << 13), in _set_rx_dck()
1702 rtw89_phy_write32_set(rtwdev, R_S0_RXDC2 + (path << 13), B_S0_RXDC2_MEN); in _set_rx_dck()
1703 rtw89_phy_write32_mask(rtwdev, R_S0_RXDC2 + (path << 13), in _set_rx_dck()
1712 rtw89_write_rf(rtwdev, path, RR_DCK2, RR_DCK2_CYCLE, 0x3f); in _set_rx_dck()
1713 rtw89_write_rf(rtwdev, path, RR_DCK1, RR_DCK1_SEL, is_afe); in _set_rx_dck()
1717 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x0); in _set_rx_dck()
1718 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x1); in _set_rx_dck()
1724 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_LV, 0x0); in _set_rx_dck()
1727 rtw89_phy_write32_clr(rtwdev, R_P0_NRBW + (path << 13), B_P0_NRBW_DBG); in _set_rx_dck()
1728 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK + (path << 13), in _set_rx_dck()
1736 u8 path, kpath, dck_tune; in _rx_dck() local
1746 for (path = 0; path < 2; path++) { in _rx_dck()
1747 if (!(kpath & BIT(path))) in _rx_dck()
1750 rf_reg5 = rtw89_read_rf(rtwdev, path, RR_RSV1, RFREG_MASK); in _rx_dck()
1751 dck_tune = (u8)rtw89_read_rf(rtwdev, path, RR_DCK, RR_DCK_FINE); in _rx_dck()
1753 if (rtwdev->is_tssi_mode[path]) { in _rx_dck()
1754 addr = 0x5818 + (path << 13); in _rx_dck()
1759 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0); in _rx_dck()
1760 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_FINE, 0x0); in _rx_dck()
1761 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX); in _rx_dck()
1762 _set_rx_dck(rtwdev, phy, path, is_afe); in _rx_dck()
1763 rtw89_write_rf(rtwdev, path, RR_DCK, RR_DCK_FINE, dck_tune); in _rx_dck()
1764 rtw89_write_rf(rtwdev, path, RR_RSV1, RFREG_MASK, rf_reg5); in _rx_dck()
1766 if (rtwdev->is_tssi_mode[path]) { in _rx_dck()
1767 addr = 0x5818 + (path << 13); in _rx_dck()
1790 enum rtw89_rf_path path, bool is_bybb) in _rf_direct_cntrl() argument
1793 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x1); in _rf_direct_cntrl()
1795 rtw89_write_rf(rtwdev, path, RR_RSV1, RR_RSV1_RST, 0x0); in _rf_direct_cntrl()
1799 enum rtw89_rf_path path, bool off);
1803 u8 path) in _dpk_bkup_kip() argument
1808 reg_bkup[path][i] = rtw89_phy_read32_mask(rtwdev, in _dpk_bkup_kip()
1809 reg[i] + (path << 8), in _dpk_bkup_kip()
1812 reg[i] + (path << 8), reg_bkup[path][i]); in _dpk_bkup_kip()
1817 u32 reg_bkup[][RTW8852A_DPK_KIP_REG_NUM], u8 path) in _dpk_reload_kip() argument
1822 rtw89_phy_write32_mask(rtwdev, reg[i] + (path << 8), in _dpk_reload_kip()
1823 MASKDWORD, reg_bkup[path][i]); in _dpk_reload_kip()
1825 reg[i] + (path << 8), reg_bkup[path][i]); in _dpk_reload_kip()
1830 enum rtw89_rf_path path, enum rtw8852a_dpk_id id) in _dpk_one_shot() argument
1832 u8 phy_map = rtw89_btc_path_phymap(rtwdev, phy, path); in _dpk_one_shot()
1837 dpk_cmd = (u16)((id << 8) | (0x19 + (path << 4))); in _dpk_one_shot()
1871 enum rtw89_rf_path path) in _dpk_rx_dck() argument
1873 rtw89_write_rf(rtwdev, path, RR_RXBB2, RR_EN_TIA_IDA, 0x3); in _dpk_rx_dck()
1874 _set_rx_dck(rtwdev, phy, path, false); in _dpk_rx_dck()
1879 enum rtw89_rf_path path) in _dpk_information() argument
1883 u8 kidx = dpk->cur_idx[path]; in _dpk_information()
1885 dpk->bp[path][kidx].band = chan->band_type; in _dpk_information()
1886 dpk->bp[path][kidx].ch = chan->channel; in _dpk_information()
1887 dpk->bp[path][kidx].bw = chan->band_width; in _dpk_information()
1891 path, dpk->cur_idx[path], phy, in _dpk_information()
1892 rtwdev->is_tssi_mode[path] ? "on" : "off", in _dpk_information()
1894 dpk->bp[path][kidx].band == 0 ? "2G" : in _dpk_information()
1895 dpk->bp[path][kidx].band == 1 ? "5G" : "6G", in _dpk_information()
1896 dpk->bp[path][kidx].ch, in _dpk_information()
1897 dpk->bp[path][kidx].bw == 0 ? "20M" : in _dpk_information()
1898 dpk->bp[path][kidx].bw == 1 ? "40M" : "80M"); in _dpk_information()
1903 enum rtw89_rf_path path, u8 kpath) in _dpk_bb_afe_setting() argument
1934 enum rtw89_rf_path path, u8 kpath) in _dpk_bb_afe_restore() argument
1954 enum rtw89_rf_path path, bool is_pause) in _dpk_tssi_pause() argument
1956 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK + (path << 13), in _dpk_tssi_pause()
1959 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d TSSI %s\n", path, in _dpk_tssi_pause()
1964 enum rtw89_rf_path path, u8 kidx) in _dpk_kip_setting() argument
1969 rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), MASKDWORD, 0xce000a08); in _dpk_kip_setting()
1971 rtw89_phy_write32_mask(rtwdev, R_NCTL_CFG, B_NCTL_CFG_SPAGE, path); /*subpage_id*/ in _dpk_kip_setting()
1972 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0 + (path << 8) + (kidx << 2), in _dpk_kip_setting()
1974 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2), in _dpk_kip_setting()
1978 path, kidx); in _dpk_kip_setting()
1982 enum rtw89_rf_path path) in _dpk_kip_restore() argument
1986 rtw89_phy_write32_mask(rtwdev, R_CFIR_SYS + (path << 8), MASKDWORD, 0x10010000); in _dpk_kip_restore()
1990 rtw89_phy_write32_mask(rtwdev, R_DPD_COM + (path << 8), BIT(15), 0x1); in _dpk_kip_restore()
1992 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d restore KIP\n", path); in _dpk_kip_restore()
1997 enum rtw89_rf_path path) in _dpk_lbk_rxiqk() argument
2001 cur_rxbb = (u8)rtw89_read_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXBB); in _dpk_lbk_rxiqk()
2005 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, 0xc); in _dpk_lbk_rxiqk()
2006 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_PLLEN, 0x1); in _dpk_lbk_rxiqk()
2007 rtw89_write_rf(rtwdev, path, RR_RXPOW, RR_RXPOW_IQK, 0x2); in _dpk_lbk_rxiqk()
2008 rtw89_write_rf(rtwdev, path, RR_RSV4, RFREG_MASK, in _dpk_lbk_rxiqk()
2009 rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK)); in _dpk_lbk_rxiqk()
2010 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_OFF, 0x13); in _dpk_lbk_rxiqk()
2011 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0); in _dpk_lbk_rxiqk()
2012 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x1); in _dpk_lbk_rxiqk()
2016 rtw89_write_rf(rtwdev, path, RR_RXIQGEN, RR_RXIQGEN_ATTL, 0x1f); in _dpk_lbk_rxiqk()
2019 rtw89_write_rf(rtwdev, path, RR_RXIQGEN, RR_RXIQGEN_ATTH, 0x3); in _dpk_lbk_rxiqk()
2021 rtw89_write_rf(rtwdev, path, RR_RXIQGEN, RR_RXIQGEN_ATTH, 0x1); in _dpk_lbk_rxiqk()
2023 rtw89_write_rf(rtwdev, path, RR_RXIQGEN, RR_RXIQGEN_ATTH, 0x0); in _dpk_lbk_rxiqk()
2027 _dpk_one_shot(rtwdev, phy, path, LBK_RXIQK); in _dpk_lbk_rxiqk()
2029 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d LBK RXIQC = 0x%x\n", path, in _dpk_lbk_rxiqk()
2032 rtw89_write_rf(rtwdev, path, RR_RXK, RR_RXK_PLLEN, 0x0); in _dpk_lbk_rxiqk()
2033 rtw89_write_rf(rtwdev, path, RR_RXPOW, RR_RXPOW_IQK, 0x0); in _dpk_lbk_rxiqk()
2034 rtw89_write_rf(rtwdev, path, RR_RXKPLL, RR_RXKPLL_POW, 0x0); /*POW IQKPLL*/ in _dpk_lbk_rxiqk()
2035 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_DPK); in _dpk_lbk_rxiqk()
2041 enum rtw89_rf_path path) in _dpk_get_thermal() argument
2045 dpk->bp[path][kidx].ther_dpk = in _dpk_get_thermal()
2046 ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]); in _dpk_get_thermal()
2049 dpk->bp[path][kidx].ther_dpk); in _dpk_get_thermal()
2053 enum rtw89_rf_path path) in _dpk_set_tx_pwr() argument
2057 rtw89_write_rf(rtwdev, path, RR_MODOPT, RFREG_MASK, txagc_ori); in _dpk_set_tx_pwr()
2063 enum rtw89_rf_path path, u8 kidx) in _dpk_rf_setting() argument
2067 if (dpk->bp[path][kidx].band == RTW89_BAND_2G) { in _dpk_rf_setting()
2068 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_DPK, 0x280b); in _dpk_rf_setting()
2069 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_ATTC, 0x0); in _dpk_rf_setting()
2070 rtw89_write_rf(rtwdev, path, RR_RXBB, RR_RXBB_ATTR, 0x4); in _dpk_rf_setting()
2071 rtw89_write_rf(rtwdev, path, RR_MIXER, RR_MIXER_GN, 0x0); in _dpk_rf_setting()
2073 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_DPK, 0x282e); in _dpk_rf_setting()
2074 rtw89_write_rf(rtwdev, path, RR_BIASA2, RR_BIASA2_LB, 0x7); in _dpk_rf_setting()
2075 rtw89_write_rf(rtwdev, path, RR_TXATANK, RR_TXATANK_LBSW, 0x3); in _dpk_rf_setting()
2076 rtw89_write_rf(rtwdev, path, RR_RXA, RR_RXA_DPK, 0x3); in _dpk_rf_setting()
2078 rtw89_write_rf(rtwdev, path, RR_RCKD, RR_RCKD_BW, 0x1); in _dpk_rf_setting()
2079 rtw89_write_rf(rtwdev, path, RR_BTC, RR_BTC_TXBB, dpk->bp[path][kidx].bw + 1); in _dpk_rf_setting()
2080 rtw89_write_rf(rtwdev, path, RR_BTC, RR_BTC_RXBB, 0x0); in _dpk_rf_setting()
2084 rtw89_read_rf(rtwdev, path, RR_MOD, RFREG_MASK), in _dpk_rf_setting()
2085 rtw89_read_rf(rtwdev, path, RR_MODOPT, RFREG_MASK), in _dpk_rf_setting()
2086 rtw89_read_rf(rtwdev, path, RR_BTC, RFREG_MASK)); in _dpk_rf_setting()
2090 enum rtw89_rf_path path, bool is_manual) in _dpk_manual_txcfir() argument
2095 rtw89_phy_write32_mask(rtwdev, R_KIP + (path << 8), B_KIP_RFGAIN, 0x1); in _dpk_manual_txcfir()
2096 tmp_pad = (u8)rtw89_read_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_PAD); in _dpk_manual_txcfir()
2097 rtw89_phy_write32_mask(rtwdev, R_RFGAIN + (path << 8), in _dpk_manual_txcfir()
2100 tmp_txbb = (u8)rtw89_read_rf(rtwdev, path, RR_GAINTX, RR_GAINTX_BB); in _dpk_manual_txcfir()
2101 rtw89_phy_write32_mask(rtwdev, R_RFGAIN + (path << 8), in _dpk_manual_txcfir()
2104 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), in _dpk_manual_txcfir()
2106 rtw89_phy_write32_clr(rtwdev, R_LOAD_COEF + (path << 8), in _dpk_manual_txcfir()
2109 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), BIT(1), 0x1); in _dpk_manual_txcfir()
2115 rtw89_phy_write32_clr(rtwdev, R_KIP + (path << 8), B_KIP_RFGAIN); in _dpk_manual_txcfir()
2122 enum rtw89_rf_path path, bool is_bypass) in _dpk_bypass_rxcfir() argument
2125 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), in _dpk_bypass_rxcfir()
2127 rtw89_phy_write32_mask(rtwdev, R_RXIQC + (path << 8), in _dpk_bypass_rxcfir()
2130 "[DPK] Bypass RXIQC (0x8%d3c = 0x%x)\n", 1 + path, in _dpk_bypass_rxcfir()
2131 rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), in _dpk_bypass_rxcfir()
2134 rtw89_phy_write32_clr(rtwdev, R_RXIQC + (path << 8), B_RXIQC_BYPASS2); in _dpk_bypass_rxcfir()
2135 rtw89_phy_write32_clr(rtwdev, R_RXIQC + (path << 8), B_RXIQC_BYPASS); in _dpk_bypass_rxcfir()
2137 "[DPK] restore 0x8%d3c = 0x%x\n", 1 + path, in _dpk_bypass_rxcfir()
2138 rtw89_phy_read32_mask(rtwdev, R_RXIQC + (path << 8), in _dpk_bypass_rxcfir()
2144 void _dpk_tpg_sel(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, u8 kidx) in _dpk_tpg_sel() argument
2148 if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80) in _dpk_tpg_sel()
2150 else if (dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40) in _dpk_tpg_sel()
2156 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_80 ? "80M" : in _dpk_tpg_sel()
2157 dpk->bp[path][kidx].bw == RTW89_CHANNEL_WIDTH_40 ? "40M" : "20M"); in _dpk_tpg_sel()
2161 enum rtw89_rf_path path, u8 kidx, u8 gain) in _dpk_table_select() argument
2166 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0 + (path << 8), MASKBYTE3, val); in _dpk_table_select()
2173 enum rtw89_rf_path path) in _dpk_sync_check() argument
2188 "[DPK] S%d Corr_idx / Corr_val = %d / %d\n", path, corr_idx, in _dpk_sync_check()
2191 dpk->corr_idx[path][0] = corr_idx; in _dpk_sync_check()
2192 dpk->corr_val[path][0] = corr_val; in _dpk_sync_check()
2203 path, dc_i, dc_q); in _dpk_sync_check()
2205 dpk->dc_i[path][0] = dc_i; in _dpk_sync_check()
2206 dpk->dc_q[path][0] = dc_q; in _dpk_sync_check()
2216 enum rtw89_rf_path path, u8 kidx) in _dpk_sync() argument
2218 _dpk_tpg_sel(rtwdev, path, kidx); in _dpk_sync()
2219 _dpk_one_shot(rtwdev, phy, path, SYNC); in _dpk_sync()
2220 return _dpk_sync_check(rtwdev, path); /*1= fail*/ in _dpk_sync()
2271 enum rtw89_phy_idx phy, enum rtw89_rf_path path, in _dpk_gainloss() argument
2274 _dpk_table_select(rtwdev, path, kidx, 1); in _dpk_gainloss()
2275 _dpk_one_shot(rtwdev, phy, path, GAIN_LOSS); in _dpk_gainloss()
2283 enum rtw89_rf_path path, s8 gain_offset) in _dpk_set_offset() argument
2287 txagc = (u8)rtw89_read_rf(rtwdev, path, RR_MODOPT, RFREG_MASK); in _dpk_set_offset()
2296 rtw89_write_rf(rtwdev, path, RR_MODOPT, RFREG_MASK, txagc); in _dpk_set_offset()
2351 enum rtw89_rf_path path, u8 kidx, u8 init_txagc, in _dpk_agc() argument
2374 if (_dpk_sync(rtwdev, phy, path, kidx)) { in _dpk_agc()
2389 tmp_rxbb = (u8)rtw89_read_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXBB); in _dpk_agc()
2402 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_M_RXBB, tmp_rxbb); in _dpk_agc()
2408 _dpk_bypass_rxcfir(rtwdev, path, true); in _dpk_agc()
2410 _dpk_lbk_rxiqk(rtwdev, phy, path); in _dpk_agc()
2421 _dpk_gainloss(rtwdev, phy, path, kidx); in _dpk_agc()
2439 tmp_txagc = _dpk_set_offset(rtwdev, path, 3); in _dpk_agc()
2451 tmp_txagc = _dpk_set_offset(rtwdev, path, -2); in _dpk_agc()
2458 tmp_txagc = _dpk_set_offset(rtwdev, path, tmp_gl_idx); in _dpk_agc()
2505 enum rtw89_rf_path path, u8 kidx, u8 gain) in _dpk_idl_mpa() argument
2508 _dpk_table_select(rtwdev, path, kidx, 1); in _dpk_idl_mpa()
2509 _dpk_one_shot(rtwdev, phy, path, MDPK_IDL); in _dpk_idl_mpa()
2513 enum rtw89_rf_path path, u8 kidx, u8 gain, in _dpk_fill_result() argument
2521 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8), B_COEF_SEL_MDPD, kidx); in _dpk_fill_result()
2527 dpk->bp[path][kidx].txagc_dpk = txagc; in _dpk_fill_result()
2528 rtw89_phy_write32_mask(rtwdev, R_TXAGC_RFK + (path << 8), in _dpk_fill_result()
2531 dpk->bp[path][kidx].pwsf = pwsf; in _dpk_fill_result()
2532 rtw89_phy_write32_mask(rtwdev, R_DPD_BND + (path << 8) + (kidx << 2), in _dpk_fill_result()
2535 rtw89_phy_write32_mask(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD, 0x1); in _dpk_fill_result()
2536 rtw89_phy_write32_clr(rtwdev, R_LOAD_COEF + (path << 8), B_LOAD_COEF_MDPD); in _dpk_fill_result()
2538 dpk->bp[path][kidx].gs = gs; in _dpk_fill_result()
2539 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2), in _dpk_fill_result()
2542 rtw89_phy_write32_clr(rtwdev, R_DPD_V1 + (path << 8), MASKDWORD); in _dpk_fill_result()
2548 enum rtw89_rf_path path) in _dpk_reload_check() argument
2559 if (cur_band != dpk->bp[path][idx].band || in _dpk_reload_check()
2560 cur_ch != dpk->bp[path][idx].ch) in _dpk_reload_check()
2563 rtw89_phy_write32_mask(rtwdev, R_COEF_SEL + (path << 8), in _dpk_reload_check()
2565 dpk->cur_idx[path] = idx; in _dpk_reload_check()
2568 "[DPK] reload S%d[%d] success\n", path, idx); in _dpk_reload_check()
2575 enum rtw89_rf_path path, u8 gain) in _dpk_main() argument
2578 u8 txagc = 0, kidx = dpk->cur_idx[path]; in _dpk_main()
2582 "[DPK] ========= S%d[%d] DPK Start =========\n", path, in _dpk_main()
2585 _rf_direct_cntrl(rtwdev, path, false); in _dpk_main()
2586 txagc = _dpk_set_tx_pwr(rtwdev, gain, path); in _dpk_main()
2587 _dpk_rf_setting(rtwdev, gain, path, kidx); in _dpk_main()
2588 _dpk_rx_dck(rtwdev, phy, path); in _dpk_main()
2590 _dpk_kip_setting(rtwdev, path, kidx); in _dpk_main()
2591 _dpk_manual_txcfir(rtwdev, path, true); in _dpk_main()
2592 txagc = _dpk_agc(rtwdev, phy, path, kidx, txagc, false); in _dpk_main()
2595 _dpk_get_thermal(rtwdev, kidx, path); in _dpk_main()
2597 _dpk_idl_mpa(rtwdev, phy, path, kidx, gain); in _dpk_main()
2598 rtw89_write_rf(rtwdev, path, RR_MOD, RR_MOD_MASK, RR_MOD_V_RX); in _dpk_main()
2599 _dpk_fill_result(rtwdev, path, kidx, gain, txagc); in _dpk_main()
2600 _dpk_manual_txcfir(rtwdev, path, false); in _dpk_main()
2603 dpk->bp[path][kidx].path_ok = true; in _dpk_main()
2605 dpk->bp[path][kidx].path_ok = false; in _dpk_main()
2607 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d] DPK %s\n", path, kidx, in _dpk_main()
2621 u8 path; in _dpk_cal_select() local
2625 for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) { in _dpk_cal_select()
2626 if (!(kpath & BIT(path))) in _dpk_cal_select()
2629 reloaded[path] = _dpk_reload_check(rtwdev, phy, path); in _dpk_cal_select()
2630 if (!reloaded[path] && dpk->bp[path][0].ch != 0) in _dpk_cal_select()
2631 dpk->cur_idx[path] = !dpk->cur_idx[path]; in _dpk_cal_select()
2633 _dpk_onoff(rtwdev, path, false); in _dpk_cal_select()
2636 for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) in _dpk_cal_select()
2637 dpk->cur_idx[path] = 0; in _dpk_cal_select()
2647 for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) { in _dpk_cal_select()
2648 if (!(kpath & BIT(path)) || reloaded[path]) in _dpk_cal_select()
2650 if (rtwdev->is_tssi_mode[path]) in _dpk_cal_select()
2651 _dpk_tssi_pause(rtwdev, path, true); in _dpk_cal_select()
2652 _dpk_bkup_kip(rtwdev, kip_reg, kip_bkup, path); in _dpk_cal_select()
2653 _rfk_backup_rf_reg(rtwdev, &backup_rf_val[path][0], path); in _dpk_cal_select()
2654 _dpk_information(rtwdev, phy, path); in _dpk_cal_select()
2657 _dpk_bb_afe_setting(rtwdev, phy, path, kpath); in _dpk_cal_select()
2659 for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) { in _dpk_cal_select()
2660 if (!(kpath & BIT(path)) || reloaded[path]) in _dpk_cal_select()
2663 is_fail = _dpk_main(rtwdev, phy, path, 1); in _dpk_cal_select()
2664 _dpk_onoff(rtwdev, path, is_fail); in _dpk_cal_select()
2667 _dpk_bb_afe_restore(rtwdev, phy, path, kpath); in _dpk_cal_select()
2670 for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) { in _dpk_cal_select()
2671 if (!(kpath & BIT(path)) || reloaded[path]) in _dpk_cal_select()
2674 _dpk_kip_restore(rtwdev, path); in _dpk_cal_select()
2675 _dpk_reload_kip(rtwdev, kip_reg, kip_bkup, path); in _dpk_cal_select()
2676 _rfk_restore_rf_reg(rtwdev, &backup_rf_val[path][0], path); in _dpk_cal_select()
2677 if (rtwdev->is_tssi_mode[path]) in _dpk_cal_select()
2678 _dpk_tssi_pause(rtwdev, path, false); in _dpk_cal_select()
2702 u8 path, kpath; in _dpk_force_bypass() local
2706 for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) { in _dpk_force_bypass()
2707 if (kpath & BIT(path)) in _dpk_force_bypass()
2708 _dpk_onoff(rtwdev, path, true); in _dpk_force_bypass()
2726 enum rtw89_rf_path path, bool off) in _dpk_onoff() argument
2729 u8 val, kidx = dpk->cur_idx[path]; in _dpk_onoff()
2731 val = dpk->is_dpk_enable && !off && dpk->bp[path][kidx].path_ok; in _dpk_onoff()
2733 rtw89_phy_write32_mask(rtwdev, R_DPD_CH0A + (path << 8) + (kidx << 2), in _dpk_onoff()
2736 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DPK] S%d[%d] DPK %s !!!\n", path, in _dpk_onoff()
2744 u8 path, kidx; in _dpk_track() local
2751 for (path = 0; path < RTW8852A_DPK_RF_PATH; path++) { in _dpk_track()
2752 kidx = dpk->cur_idx[path]; in _dpk_track()
2756 path, kidx, dpk->bp[path][kidx].ch); in _dpk_track()
2758 cur_ther = ewma_thermal_read(&rtwdev->phystat.avg_thermal[path]); in _dpk_track()
2763 if (dpk->bp[path][kidx].ch != 0 && cur_ther != 0) in _dpk_track()
2764 delta_ther[path] = dpk->bp[path][kidx].ther_dpk - cur_ther; in _dpk_track()
2766 if (dpk->bp[path][kidx].band == RTW89_BAND_2G) in _dpk_track()
2767 delta_ther[path] = delta_ther[path] * 3 / 2; in _dpk_track()
2769 delta_ther[path] = delta_ther[path] * 5 / 2; in _dpk_track()
2771 txagc_rf = (u8)rtw89_phy_read32_mask(rtwdev, R_TXAGC_BB + (path << 13), in _dpk_track()
2774 if (rtwdev->is_tssi_mode[path]) { in _dpk_track()
2775 trk_idx = (u8)rtw89_read_rf(rtwdev, path, RR_TXA, RR_TXA_TRK); in _dpk_track()
2783 R_TXAGC_BB + (path << 13), in _dpk_track()
2787 R_TXAGC_TP + (path << 13), in _dpk_track()
2796 R_TXAGC_BB + (path << 13), in _dpk_track()
2801 txagc_ofst, delta_ther[path]); in _dpk_track()
2803 if (rtw89_phy_read32_mask(rtwdev, R_DPD_COM + (path << 8), in _dpk_track()
2808 ini_diff = txagc_ofst + delta_ther[path]; in _dpk_track()
2810 if (rtw89_phy_read32_mask(rtwdev, R_P0_TXDPD + (path << 13), in _dpk_track()
2812 pwsf[0] = dpk->bp[path][kidx].pwsf + txagc_bb_tp - in _dpk_track()
2814 tssi_info->extra_ofst[path]; in _dpk_track()
2815 pwsf[1] = dpk->bp[path][kidx].pwsf + txagc_bb_tp - in _dpk_track()
2817 tssi_info->extra_ofst[path]; in _dpk_track()
2819 pwsf[0] = dpk->bp[path][kidx].pwsf + ini_diff + in _dpk_track()
2820 tssi_info->extra_ofst[path]; in _dpk_track()
2821 pwsf[1] = dpk->bp[path][kidx].pwsf + ini_diff + in _dpk_track()
2822 tssi_info->extra_ofst[path]; in _dpk_track()
2826 pwsf[0] = (dpk->bp[path][kidx].pwsf + delta_ther[path]) & 0x1ff; in _dpk_track()
2827 pwsf[1] = (dpk->bp[path][kidx].pwsf + delta_ther[path]) & 0x1ff; in _dpk_track()
2836 rtw89_phy_write32_mask(rtwdev, R_DPD_BND + (path << 8) + (kidx << 2), in _dpk_track()
2838 rtw89_phy_write32_mask(rtwdev, R_DPD_BND + (path << 8) + (kidx << 2), in _dpk_track()
2845 enum rtw89_rf_path path) in _tssi_rf_setting() argument
2851 rtw89_write_rf(rtwdev, path, RR_TXPOW, RR_TXPOW_TXG, 0x1); in _tssi_rf_setting()
2853 rtw89_write_rf(rtwdev, path, RR_TXPOW, RR_TXPOW_TXA, 0x1); in _tssi_rf_setting()
2868 enum rtw89_rf_path path) in _tssi_ini_txpwr_ctrl_bb() argument
2873 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _tssi_ini_txpwr_ctrl_bb()
2883 enum rtw89_rf_path path) in _tssi_ini_txpwr_ctrl_bb_he_tb() argument
2885 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _tssi_ini_txpwr_ctrl_bb_he_tb()
2891 enum rtw89_rf_path path) in _tssi_set_dck() argument
2893 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _tssi_set_dck()
2899 enum rtw89_rf_path path) in _tssi_set_tmeter_tbl() argument
2953 if (path == RF_PATH_A) { in _tssi_set_tmeter_tbl()
3057 enum rtw89_rf_path path) in _tssi_set_dac_gain_tbl() argument
3059 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _tssi_set_dac_gain_tbl()
3065 enum rtw89_rf_path path) in _tssi_slope_cal_org() argument
3067 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _tssi_slope_cal_org()
3073 enum rtw89_rf_path path) in _tssi_set_rf_gap_tbl() argument
3075 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _tssi_set_rf_gap_tbl()
3081 enum rtw89_rf_path path) in _tssi_set_slope() argument
3083 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _tssi_set_slope()
3089 enum rtw89_rf_path path) in _tssi_set_track() argument
3091 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _tssi_set_track()
3098 enum rtw89_rf_path path) in _tssi_set_txagc_offset_mv_avg() argument
3100 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _tssi_set_txagc_offset_mv_avg()
3106 enum rtw89_rf_path path) in _tssi_pak() argument
3114 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _tssi_pak()
3119 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _tssi_pak()
3124 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _tssi_pak()
3129 rtw89_rfk_parser_by_cond(rtwdev, path == RF_PATH_A, in _tssi_pak()
3282 enum rtw89_rf_path path) in _tssi_get_ofdm_de() argument
3296 path, gidx); in _tssi_get_ofdm_de()
3301 de_1st = tssi_info->tssi_mcs[path][gidx_1st]; in _tssi_get_ofdm_de()
3302 de_2nd = tssi_info->tssi_mcs[path][gidx_2nd]; in _tssi_get_ofdm_de()
3307 path, val, de_1st, de_2nd); in _tssi_get_ofdm_de()
3309 val = tssi_info->tssi_mcs[path][gidx]; in _tssi_get_ofdm_de()
3312 "[TSSI][TRIM]: path=%d mcs de=%d\n", path, val); in _tssi_get_ofdm_de()
3320 enum rtw89_rf_path path) in _tssi_get_ofdm_trim_de() argument
3334 path, tgidx); in _tssi_get_ofdm_trim_de()
3339 tde_1st = tssi_info->tssi_trim[path][tgidx_1st]; in _tssi_get_ofdm_trim_de()
3340 tde_2nd = tssi_info->tssi_trim[path][tgidx_2nd]; in _tssi_get_ofdm_trim_de()
3345 path, val, tde_1st, tde_2nd); in _tssi_get_ofdm_trim_de()
3347 val = tssi_info->tssi_trim[path][tgidx]; in _tssi_get_ofdm_trim_de()
3351 path, val); in _tssi_get_ofdm_trim_de()
3429 u8 path; in _tssi_track() local
3442 for (path = RF_PATH_A; path < RF_PATH_NUM_8852A; path++) { in _tssi_track()
3443 if (!tssi_info->tssi_tracking_check[path]) { in _tssi_track()
3449 R_TSSI_THER + (path << 13), in _tssi_track()
3452 if (cur_ther == 0 || tssi_info->base_thermal[path] == 0) in _tssi_track()
3455 delta_ther = cur_ther - tssi_info->base_thermal[path]; in _tssi_track()
3459 tssi_info->extra_ofst[path] = gain_offset; in _tssi_track()
3463 tssi_info->base_thermal[path], gain_offset, path); in _tssi_track()
3473 rtw89_phy_write32_mask(rtwdev, R_DPD_OFT_EN + (path << 13), in _tssi_track()
3476 rtw89_phy_write32_mask(rtwdev, R_TXGAIN_SCALE + (path << 13), in _tssi_track()
3479 rtw89_phy_write32_mask(rtwdev, R_DPD_OFT_ADDR + (path << 13), in _tssi_track()
3482 rtw89_phy_write32_mask(rtwdev, R_TXGAIN_SCALE + (path << 13), in _tssi_track()
3527 u8 path, s16 pwr_dbm, u8 enable) in _tssi_hw_tx() argument
3530 rtw8852a_bb_cfg_tx_path(rtwdev, path); in _tssi_hw_tx()
3624 u8 path; in rtw8852a_rck() local
3626 for (path = 0; path < 2; path++) in rtw8852a_rck()
3627 _rck(rtwdev, path); in rtw8852a_rck()