Lines Matching refs:WL18XX_REGISTERS_BASE
11 #define WL18XX_REGISTERS_BASE 0x00800000 macro
31 #define WL18XX_SDIO_WSPI_BASE (WL18XX_REGISTERS_BASE)
32 #define WL18XX_REG_CONFIG_BASE (WL18XX_REGISTERS_BASE + 0x02000)
33 #define WL18XX_WGCM_REGS_BASE (WL18XX_REGISTERS_BASE + 0x03000)
34 #define WL18XX_ENC_BASE (WL18XX_REGISTERS_BASE + 0x04000)
35 #define WL18XX_INTERRUPT_BASE (WL18XX_REGISTERS_BASE + 0x05000)
36 #define WL18XX_UART_BASE (WL18XX_REGISTERS_BASE + 0x06000)
37 #define WL18XX_WELP_BASE (WL18XX_REGISTERS_BASE + 0x07000)
38 #define WL18XX_TCP_CKSM_BASE (WL18XX_REGISTERS_BASE + 0x08000)
39 #define WL18XX_FIFO_BASE (WL18XX_REGISTERS_BASE + 0x09000)
40 #define WL18XX_OCP_BRIDGE_BASE (WL18XX_REGISTERS_BASE + 0x0A000)
41 #define WL18XX_PMAC_RX_BASE (WL18XX_REGISTERS_BASE + 0x14800)
42 #define WL18XX_PMAC_ACM_BASE (WL18XX_REGISTERS_BASE + 0x14C00)
43 #define WL18XX_PMAC_TX_BASE (WL18XX_REGISTERS_BASE + 0x15000)
44 #define WL18XX_PMAC_CSR_BASE (WL18XX_REGISTERS_BASE + 0x15400)
46 #define WL18XX_REG_ECPU_CONTROL (WL18XX_REGISTERS_BASE + 0x02004)
47 #define WL18XX_REG_INTERRUPT_NO_CLEAR (WL18XX_REGISTERS_BASE + 0x050E8)
48 #define WL18XX_REG_INTERRUPT_ACK (WL18XX_REGISTERS_BASE + 0x050F0)
49 #define WL18XX_REG_INTERRUPT_TRIG (WL18XX_REGISTERS_BASE + 0x5074)
50 #define WL18XX_REG_INTERRUPT_TRIG_H (WL18XX_REGISTERS_BASE + 0x5078)
51 #define WL18XX_REG_INTERRUPT_MASK (WL18XX_REGISTERS_BASE + 0x0050DC)
53 #define WL18XX_REG_CHIP_ID_B (WL18XX_REGISTERS_BASE + 0x01542C)
59 #define WL18XX_SCR_PAD0 (WL18XX_REGISTERS_BASE + 0x0154EC)
60 #define WL18XX_SCR_PAD1 (WL18XX_REGISTERS_BASE + 0x0154F0)
61 #define WL18XX_SCR_PAD2 (WL18XX_REGISTERS_BASE + 0x0154F4)
62 #define WL18XX_SCR_PAD3 (WL18XX_REGISTERS_BASE + 0x0154F8)
63 #define WL18XX_SCR_PAD4 (WL18XX_REGISTERS_BASE + 0x0154FC)
64 #define WL18XX_SCR_PAD4_SET (WL18XX_REGISTERS_BASE + 0x015504)
65 #define WL18XX_SCR_PAD4_CLR (WL18XX_REGISTERS_BASE + 0x015500)
66 #define WL18XX_SCR_PAD5 (WL18XX_REGISTERS_BASE + 0x015508)
67 #define WL18XX_SCR_PAD5_SET (WL18XX_REGISTERS_BASE + 0x015510)
68 #define WL18XX_SCR_PAD5_CLR (WL18XX_REGISTERS_BASE + 0x01550C)
69 #define WL18XX_SCR_PAD6 (WL18XX_REGISTERS_BASE + 0x015514)
70 #define WL18XX_SCR_PAD7 (WL18XX_REGISTERS_BASE + 0x015518)
71 #define WL18XX_SCR_PAD8 (WL18XX_REGISTERS_BASE + 0x01551C)
72 #define WL18XX_SCR_PAD9 (WL18XX_REGISTERS_BASE + 0x015520)
75 #define WL18XX_SPARE_A1 (WL18XX_REGISTERS_BASE + 0x002194)
76 #define WL18XX_SPARE_A2 (WL18XX_REGISTERS_BASE + 0x002198)
77 #define WL18XX_SPARE_A3 (WL18XX_REGISTERS_BASE + 0x00219C)
78 #define WL18XX_SPARE_A4 (WL18XX_REGISTERS_BASE + 0x0021A0)
79 #define WL18XX_SPARE_A5 (WL18XX_REGISTERS_BASE + 0x0021A4)
80 #define WL18XX_SPARE_A6 (WL18XX_REGISTERS_BASE + 0x0021A8)
81 #define WL18XX_SPARE_A7 (WL18XX_REGISTERS_BASE + 0x0021AC)
82 #define WL18XX_SPARE_A8 (WL18XX_REGISTERS_BASE + 0x0021B0)
83 #define WL18XX_SPARE_B1 (WL18XX_REGISTERS_BASE + 0x015524)
84 #define WL18XX_SPARE_B2 (WL18XX_REGISTERS_BASE + 0x015528)
85 #define WL18XX_SPARE_B3 (WL18XX_REGISTERS_BASE + 0x01552C)
86 #define WL18XX_SPARE_B4 (WL18XX_REGISTERS_BASE + 0x015530)
87 #define WL18XX_SPARE_B5 (WL18XX_REGISTERS_BASE + 0x015534)
88 #define WL18XX_SPARE_B6 (WL18XX_REGISTERS_BASE + 0x015538)
89 #define WL18XX_SPARE_B7 (WL18XX_REGISTERS_BASE + 0x01553C)
90 #define WL18XX_SPARE_B8 (WL18XX_REGISTERS_BASE + 0x015540)
96 #define WL18XX_WELP_ARM_COMMAND (WL18XX_REGISTERS_BASE + 0x7100)
97 #define WL18XX_ENABLE (WL18XX_REGISTERS_BASE + 0x01543C)