Lines Matching refs:pcie
176 static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off) in nwl_bridge_readl() argument
178 return readl(pcie->breg_base + off); in nwl_bridge_readl()
181 static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off) in nwl_bridge_writel() argument
183 writel(val, pcie->breg_base + off); in nwl_bridge_writel()
186 static bool nwl_pcie_link_up(struct nwl_pcie *pcie) in nwl_pcie_link_up() argument
188 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT) in nwl_pcie_link_up()
193 static bool nwl_phy_link_up(struct nwl_pcie *pcie) in nwl_phy_link_up() argument
195 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT) in nwl_phy_link_up()
200 static int nwl_wait_for_link(struct nwl_pcie *pcie) in nwl_wait_for_link() argument
202 struct device *dev = pcie->dev; in nwl_wait_for_link()
207 if (nwl_phy_link_up(pcie)) in nwl_wait_for_link()
218 struct nwl_pcie *pcie = bus->sysdata; in nwl_pcie_valid_device() local
222 if (!nwl_pcie_link_up(pcie)) in nwl_pcie_valid_device()
244 struct nwl_pcie *pcie = bus->sysdata; in nwl_pcie_map_bus() local
249 return pcie->ecam_base + PCIE_ECAM_OFFSET(bus->number, devfn, where); in nwl_pcie_map_bus()
261 struct nwl_pcie *pcie = data; in nwl_pcie_misc_handler() local
262 struct device *dev = pcie->dev; in nwl_pcie_misc_handler()
266 misc_stat = nwl_bridge_readl(pcie, MSGF_MISC_STATUS) & in nwl_pcie_misc_handler()
311 nwl_bridge_writel(pcie, misc_stat, MSGF_MISC_STATUS); in nwl_pcie_misc_handler()
319 struct nwl_pcie *pcie; in nwl_pcie_leg_handler() local
324 pcie = irq_desc_get_handler_data(desc); in nwl_pcie_leg_handler()
326 while ((status = nwl_bridge_readl(pcie, MSGF_LEG_STATUS) & in nwl_pcie_leg_handler()
329 generic_handle_domain_irq(pcie->legacy_irq_domain, bit); in nwl_pcie_leg_handler()
335 static void nwl_pcie_handle_msi_irq(struct nwl_pcie *pcie, u32 status_reg) in nwl_pcie_handle_msi_irq() argument
337 struct nwl_msi *msi = &pcie->msi; in nwl_pcie_handle_msi_irq()
341 while ((status = nwl_bridge_readl(pcie, status_reg)) != 0) { in nwl_pcie_handle_msi_irq()
343 nwl_bridge_writel(pcie, 1 << bit, status_reg); in nwl_pcie_handle_msi_irq()
352 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc); in nwl_pcie_msi_handler_high() local
355 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_HI); in nwl_pcie_msi_handler_high()
362 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc); in nwl_pcie_msi_handler_low() local
365 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_LO); in nwl_pcie_msi_handler_low()
371 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data); in nwl_mask_leg_irq() local
377 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags); in nwl_mask_leg_irq()
378 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK); in nwl_mask_leg_irq()
379 nwl_bridge_writel(pcie, (val & (~mask)), MSGF_LEG_MASK); in nwl_mask_leg_irq()
380 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags); in nwl_mask_leg_irq()
385 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data); in nwl_unmask_leg_irq() local
391 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags); in nwl_unmask_leg_irq()
392 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK); in nwl_unmask_leg_irq()
393 nwl_bridge_writel(pcie, (val | mask), MSGF_LEG_MASK); in nwl_unmask_leg_irq()
394 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags); in nwl_unmask_leg_irq()
438 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data); in nwl_compose_msi_msg() local
439 phys_addr_t msi_addr = pcie->phys_pcie_reg_base; in nwl_compose_msi_msg()
461 struct nwl_pcie *pcie = domain->host_data; in nwl_irq_domain_alloc() local
462 struct nwl_msi *msi = &pcie->msi; in nwl_irq_domain_alloc()
487 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data); in nwl_irq_domain_free() local
488 struct nwl_msi *msi = &pcie->msi; in nwl_irq_domain_free()
501 static int nwl_pcie_init_msi_irq_domain(struct nwl_pcie *pcie) in nwl_pcie_init_msi_irq_domain() argument
504 struct device *dev = pcie->dev; in nwl_pcie_init_msi_irq_domain()
506 struct nwl_msi *msi = &pcie->msi; in nwl_pcie_init_msi_irq_domain()
509 &dev_msi_domain_ops, pcie); in nwl_pcie_init_msi_irq_domain()
526 static int nwl_pcie_init_irq_domain(struct nwl_pcie *pcie) in nwl_pcie_init_irq_domain() argument
528 struct device *dev = pcie->dev; in nwl_pcie_init_irq_domain()
538 pcie->legacy_irq_domain = irq_domain_add_linear(legacy_intc_node, in nwl_pcie_init_irq_domain()
541 pcie); in nwl_pcie_init_irq_domain()
543 if (!pcie->legacy_irq_domain) { in nwl_pcie_init_irq_domain()
548 raw_spin_lock_init(&pcie->leg_mask_lock); in nwl_pcie_init_irq_domain()
549 nwl_pcie_init_msi_irq_domain(pcie); in nwl_pcie_init_irq_domain()
553 static int nwl_pcie_enable_msi(struct nwl_pcie *pcie) in nwl_pcie_enable_msi() argument
555 struct device *dev = pcie->dev; in nwl_pcie_enable_msi()
557 struct nwl_msi *msi = &pcie->msi; in nwl_pcie_enable_msi()
569 nwl_pcie_msi_handler_high, pcie); in nwl_pcie_enable_msi()
577 nwl_pcie_msi_handler_low, pcie); in nwl_pcie_enable_msi()
580 ret = nwl_bridge_readl(pcie, I_MSII_CAPABILITIES) & MSII_PRESENT; in nwl_pcie_enable_msi()
587 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) | in nwl_pcie_enable_msi()
591 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) | in nwl_pcie_enable_msi()
595 base = pcie->phys_pcie_reg_base; in nwl_pcie_enable_msi()
596 nwl_bridge_writel(pcie, lower_32_bits(base), I_MSII_BASE_LO); in nwl_pcie_enable_msi()
597 nwl_bridge_writel(pcie, upper_32_bits(base), I_MSII_BASE_HI); in nwl_pcie_enable_msi()
603 nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_HI); in nwl_pcie_enable_msi()
605 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_HI) & in nwl_pcie_enable_msi()
608 nwl_bridge_writel(pcie, MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI); in nwl_pcie_enable_msi()
614 nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_LO); in nwl_pcie_enable_msi()
616 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_LO) & in nwl_pcie_enable_msi()
619 nwl_bridge_writel(pcie, MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO); in nwl_pcie_enable_msi()
624 static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) in nwl_pcie_bridge_init() argument
626 struct device *dev = pcie->dev; in nwl_pcie_bridge_init()
631 breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT; in nwl_pcie_bridge_init()
638 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base), in nwl_pcie_bridge_init()
640 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base), in nwl_pcie_bridge_init()
644 nwl_bridge_writel(pcie, ~BREG_ENABLE_FORCE & BREG_ENABLE, in nwl_pcie_bridge_init()
648 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX0) | in nwl_pcie_bridge_init()
652 nwl_bridge_writel(pcie, SET_ISUB_CONTROL, I_ISUB_CONTROL); in nwl_pcie_bridge_init()
655 nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK, in nwl_pcie_bridge_init()
660 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX1) | in nwl_pcie_bridge_init()
663 err = nwl_wait_for_link(pcie); in nwl_pcie_bridge_init()
667 ecam_val = nwl_bridge_readl(pcie, E_ECAM_CAPABILITIES) & E_ECAM_PRESENT; in nwl_pcie_bridge_init()
674 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) | in nwl_pcie_bridge_init()
677 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) | in nwl_pcie_bridge_init()
678 (pcie->ecam_value << E_ECAM_SIZE_SHIFT), in nwl_pcie_bridge_init()
681 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base), in nwl_pcie_bridge_init()
683 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base), in nwl_pcie_bridge_init()
687 ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL); in nwl_pcie_bridge_init()
688 pcie->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT; in nwl_pcie_bridge_init()
692 ecam_val |= (pcie->last_busno << E_ECAM_SIZE_SHIFT); in nwl_pcie_bridge_init()
693 writel(ecam_val, (pcie->ecam_base + PCI_PRIMARY_BUS)); in nwl_pcie_bridge_init()
695 if (nwl_pcie_link_up(pcie)) in nwl_pcie_bridge_init()
701 pcie->irq_misc = platform_get_irq_byname(pdev, "misc"); in nwl_pcie_bridge_init()
702 if (pcie->irq_misc < 0) in nwl_pcie_bridge_init()
705 err = devm_request_irq(dev, pcie->irq_misc, in nwl_pcie_bridge_init()
707 "nwl_pcie:misc", pcie); in nwl_pcie_bridge_init()
710 pcie->irq_misc); in nwl_pcie_bridge_init()
715 nwl_bridge_writel(pcie, (u32)~MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK); in nwl_pcie_bridge_init()
718 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MISC_STATUS) & in nwl_pcie_bridge_init()
722 nwl_bridge_writel(pcie, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK); in nwl_pcie_bridge_init()
725 nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK); in nwl_pcie_bridge_init()
728 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) & in nwl_pcie_bridge_init()
732 nwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK); in nwl_pcie_bridge_init()
735 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_INTERRUPT) | in nwl_pcie_bridge_init()
741 static int nwl_pcie_parse_dt(struct nwl_pcie *pcie, in nwl_pcie_parse_dt() argument
744 struct device *dev = pcie->dev; in nwl_pcie_parse_dt()
748 pcie->breg_base = devm_ioremap_resource(dev, res); in nwl_pcie_parse_dt()
749 if (IS_ERR(pcie->breg_base)) in nwl_pcie_parse_dt()
750 return PTR_ERR(pcie->breg_base); in nwl_pcie_parse_dt()
751 pcie->phys_breg_base = res->start; in nwl_pcie_parse_dt()
754 pcie->pcireg_base = devm_ioremap_resource(dev, res); in nwl_pcie_parse_dt()
755 if (IS_ERR(pcie->pcireg_base)) in nwl_pcie_parse_dt()
756 return PTR_ERR(pcie->pcireg_base); in nwl_pcie_parse_dt()
757 pcie->phys_pcie_reg_base = res->start; in nwl_pcie_parse_dt()
760 pcie->ecam_base = devm_pci_remap_cfg_resource(dev, res); in nwl_pcie_parse_dt()
761 if (IS_ERR(pcie->ecam_base)) in nwl_pcie_parse_dt()
762 return PTR_ERR(pcie->ecam_base); in nwl_pcie_parse_dt()
763 pcie->phys_ecam_base = res->start; in nwl_pcie_parse_dt()
766 pcie->irq_intx = platform_get_irq_byname(pdev, "intx"); in nwl_pcie_parse_dt()
767 if (pcie->irq_intx < 0) in nwl_pcie_parse_dt()
768 return pcie->irq_intx; in nwl_pcie_parse_dt()
770 irq_set_chained_handler_and_data(pcie->irq_intx, in nwl_pcie_parse_dt()
771 nwl_pcie_leg_handler, pcie); in nwl_pcie_parse_dt()
784 struct nwl_pcie *pcie; in nwl_pcie_probe() local
788 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); in nwl_pcie_probe()
792 pcie = pci_host_bridge_priv(bridge); in nwl_pcie_probe()
794 pcie->dev = dev; in nwl_pcie_probe()
795 pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT; in nwl_pcie_probe()
797 err = nwl_pcie_parse_dt(pcie, pdev); in nwl_pcie_probe()
803 pcie->clk = devm_clk_get(dev, NULL); in nwl_pcie_probe()
804 if (IS_ERR(pcie->clk)) in nwl_pcie_probe()
805 return PTR_ERR(pcie->clk); in nwl_pcie_probe()
807 err = clk_prepare_enable(pcie->clk); in nwl_pcie_probe()
813 err = nwl_pcie_bridge_init(pcie); in nwl_pcie_probe()
819 err = nwl_pcie_init_irq_domain(pcie); in nwl_pcie_probe()
825 bridge->sysdata = pcie; in nwl_pcie_probe()
829 err = nwl_pcie_enable_msi(pcie); in nwl_pcie_probe()