Lines Matching refs:pci_dbg
1352 pci_dbg(dev, "Invalid power transition (from %s to %s)\n",
1529 pci_dbg(bridge, "re-enabling LTR\n");
1651 pci_dbg(dev, "saving config space at offset %#x (reading %#x)\n",
1682 pci_dbg(pdev, "restoring config space at offset %#x (was %#x, writing %#x)\n",
2515 pci_dbg(dev, "PME# %s\n", enable ? "enabled" : "disabled");
4377 pci_dbg(dev, "%s bus mastering\n",
4478 pci_dbg(dev, "cache line size of %d is not supported\n",
4507 pci_dbg(dev, "enabling Mem-Wr-Inval\n");
4996 pci_dbg(dev, "waiting %d ms for secondary bus\n", 1000 + delay);
5022 pci_dbg(dev, "waiting %d ms for downstream link\n", delay);
5025 pci_dbg(dev, "waiting %d ms for downstream link, after activation\n",