Lines Matching refs:aer

144 	int aer = dev->aer_cap;  in enable_ecrc_checking()  local
147 	if (!aer)  in enable_ecrc_checking()
150 	pci_read_config_dword(dev, aer + PCI_ERR_CAP, &reg32);  in enable_ecrc_checking()
155 	pci_write_config_dword(dev, aer + PCI_ERR_CAP, reg32);  in enable_ecrc_checking()
168 	int aer = dev->aer_cap;  in disable_ecrc_checking()  local
171 	if (!aer)  in disable_ecrc_checking()
174 	pci_read_config_dword(dev, aer + PCI_ERR_CAP, &reg32);  in disable_ecrc_checking()
176 	pci_write_config_dword(dev, aer + PCI_ERR_CAP, reg32);  in disable_ecrc_checking()
259 	int aer = dev->aer_cap;  in pci_aer_clear_nonfatal_status()  local
266 	pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);  in pci_aer_clear_nonfatal_status()
267 	pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, &sev);  in pci_aer_clear_nonfatal_status()
270 		pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status);  in pci_aer_clear_nonfatal_status()
278 	int aer = dev->aer_cap;  in pci_aer_clear_fatal_status()  local
285 	pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);  in pci_aer_clear_fatal_status()
286 	pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, &sev);  in pci_aer_clear_fatal_status()
289 		pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status);  in pci_aer_clear_fatal_status()
303 	int aer = dev->aer_cap;  in pci_aer_raw_clear_status()  local
307 	if (!aer)  in pci_aer_raw_clear_status()
313 		pci_read_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, &status);  in pci_aer_raw_clear_status()
314 		pci_write_config_dword(dev, aer + PCI_ERR_ROOT_STATUS, status);  in pci_aer_raw_clear_status()
317 	pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, &status);  in pci_aer_raw_clear_status()
318 	pci_write_config_dword(dev, aer + PCI_ERR_COR_STATUS, status);  in pci_aer_raw_clear_status()
320 	pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);  in pci_aer_raw_clear_status()
321 	pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status);  in pci_aer_raw_clear_status()
336 	int aer = dev->aer_cap;  in pci_save_aer_state()  local
340 	if (!aer)  in pci_save_aer_state()
348 	pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, cap++);  in pci_save_aer_state()
349 	pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, cap++);  in pci_save_aer_state()
350 	pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, cap++);  in pci_save_aer_state()
351 	pci_read_config_dword(dev, aer + PCI_ERR_CAP, cap++);  in pci_save_aer_state()
353 		pci_read_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, cap++);  in pci_save_aer_state()
358 	int aer = dev->aer_cap;  in pci_restore_aer_state()  local
362 	if (!aer)  in pci_restore_aer_state()
370 	pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, *cap++);  in pci_restore_aer_state()
371 	pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_SEVER, *cap++);  in pci_restore_aer_state()
372 	pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, *cap++);  in pci_restore_aer_state()
373 	pci_write_config_dword(dev, aer + PCI_ERR_CAP, *cap++);  in pci_restore_aer_state()
375 		pci_write_config_dword(dev, aer + PCI_ERR_ROOT_COMMAND, *cap++);  in pci_restore_aer_state()
776 		    struct aer_capability_regs *aer)  in cper_print_aer()  argument
783 		status = aer->cor_status;  in cper_print_aer()
784 		mask = aer->cor_mask;  in cper_print_aer()
786 		status = aer->uncor_status;  in cper_print_aer()
787 		mask = aer->uncor_mask;  in cper_print_aer()
798 	info.first_error = PCI_ERR_CAP_FEP(aer->cap_control);  in cper_print_aer()
807 			aer->uncor_severity);  in cper_print_aer()
810 		__print_tlp_header(dev, &aer->header_log);  in cper_print_aer()
813 			aer_severity, tlp_header_valid, &aer->header_log);  in cper_print_aer()
839 	int aer = dev->aer_cap;  in is_error_source()  local
874 	if (!aer)  in is_error_source()
879 		pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS, &status);  in is_error_source()
880 		pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, &mask);  in is_error_source()
882 		pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, &status);  in is_error_source()
883 		pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &mask);  in is_error_source()
957 	int aer = dev->aer_cap;  in handle_error_source()  local
964 		if (aer)  in handle_error_source()
965 			pci_write_config_dword(dev, aer + PCI_ERR_COR_STATUS,  in handle_error_source()
1064 	int aer = dev->aer_cap;  in aer_get_device_error_info()  local
1072 	if (!aer)  in aer_get_device_error_info()
1076 		pci_read_config_dword(dev, aer + PCI_ERR_COR_STATUS,  in aer_get_device_error_info()
1078 		pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK,  in aer_get_device_error_info()
1088 		pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS,  in aer_get_device_error_info()
1090 		pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK,  in aer_get_device_error_info()
1096 		pci_read_config_dword(dev, aer + PCI_ERR_CAP, &temp);  in aer_get_device_error_info()
1102 				aer + PCI_ERR_HEADER_LOG, &info->tlp.dw0);  in aer_get_device_error_info()
1104 				aer + PCI_ERR_HEADER_LOG + 4, &info->tlp.dw1);  in aer_get_device_error_info()
1106 				aer + PCI_ERR_HEADER_LOG + 8, &info->tlp.dw2);  in aer_get_device_error_info()
1108 				aer + PCI_ERR_HEADER_LOG + 12, &info->tlp.dw3);  in aer_get_device_error_info()
1214 	int aer = rp->aer_cap;  in aer_irq()  local
1217 	pci_read_config_dword(rp, aer + PCI_ERR_ROOT_STATUS, &e_src.status);  in aer_irq()
1221 	pci_read_config_dword(rp, aer + PCI_ERR_ROOT_ERR_SRC, &e_src.id);  in aer_irq()
1222 	pci_write_config_dword(rp, aer + PCI_ERR_ROOT_STATUS, e_src.status);  in aer_irq()
1239 	int aer = pdev->aer_cap;  in aer_enable_rootport()  local
1252 	pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, &reg32);  in aer_enable_rootport()
1253 	pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, reg32);  in aer_enable_rootport()
1254 	pci_read_config_dword(pdev, aer + PCI_ERR_COR_STATUS, &reg32);  in aer_enable_rootport()
1255 	pci_write_config_dword(pdev, aer + PCI_ERR_COR_STATUS, reg32);  in aer_enable_rootport()
1256 	pci_read_config_dword(pdev, aer + PCI_ERR_UNCOR_STATUS, &reg32);  in aer_enable_rootport()
1257 	pci_write_config_dword(pdev, aer + PCI_ERR_UNCOR_STATUS, reg32);  in aer_enable_rootport()
1260 	pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, &reg32);  in aer_enable_rootport()
1262 	pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, reg32);  in aer_enable_rootport()
1274 	int aer = pdev->aer_cap;  in aer_disable_rootport()  local
1278 	pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, &reg32);  in aer_disable_rootport()
1280 	pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_COMMAND, reg32);  in aer_disable_rootport()
1283 	pci_read_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, &reg32);  in aer_disable_rootport()
1284 	pci_write_config_dword(pdev, aer + PCI_ERR_ROOT_STATUS, reg32);  in aer_disable_rootport()
1353 	int aer;  in aer_root_reset()  local
1373 	aer = root ? root->aer_cap : 0;  in aer_root_reset()
1375 	if ((host->native_aer || pcie_ports_native) && aer) {  in aer_root_reset()
1377 		pci_read_config_dword(root, aer + PCI_ERR_ROOT_COMMAND, &reg32);  in aer_root_reset()
1379 		pci_write_config_dword(root, aer + PCI_ERR_ROOT_COMMAND, reg32);  in aer_root_reset()
1394 	if ((host->native_aer || pcie_ports_native) && aer) {  in aer_root_reset()
1396 		pci_read_config_dword(root, aer + PCI_ERR_ROOT_STATUS, &reg32);  in aer_root_reset()
1397 		pci_write_config_dword(root, aer + PCI_ERR_ROOT_STATUS, reg32);  in aer_root_reset()
1400 		pci_read_config_dword(root, aer + PCI_ERR_ROOT_COMMAND, &reg32);  in aer_root_reset()
1402 		pci_write_config_dword(root, aer + PCI_ERR_ROOT_COMMAND, reg32);  in aer_root_reset()